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Newbie chuman
Newbie
177 Views
Registered: ‎07-03-2018

ISE v14.7におけるOFFSET値の設定について

三栄ハイテックス 松崎と申します。

早速、質問させてください。
御社ISEv14.7を使用しまして、PLL(EIGB000_PLL_R00)の生成を行い、PLLOUTのクロック信号(clk_80m)を
使用して、入力信号に対してOFFSET遅延(6.5ns)をつけようと思ったのですが、下記のWarningが出力され、
制約は無視されるようです。
【ワーニングメッセージ】
ConstraintSystem:168 - Constraint <NET "SAD15" OFFSET = IN 6.5ns 
VALID 12.5ns BEFORE "clk_80m" RISING ;> [cube_top.ucf(656)]:
This constraint will be ignored because NET "clk_80m" could not be found or was not connected to a PAD.

上記Warningを調べてみますと、OFFSET遅延は外部入力クロックでしたら設定可能だが内部で生成したクロックについては設定が不可との事でした。
そこで質問なのですが、chip内部で生成したクロックに対してOFFSET遅延はつけれないのでしょうか?
また上記が真の場合、代替案はありますでしょうか?

以上お忙しいところ恐縮ですがご回答の程、よろしくお願いいたします。

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2 Replies
Observer ryanjohnson8
Observer
149 Views
Registered: ‎05-30-2017

Re: ISE v14.7におけるOFFSET値の設定について

ENGLISH TRANSLATION:

Hi, my name is Matsuzaki. I have a question.

I'm using ISEv14.7, PLL (EIGB000_PLL_R00) generate, generating a PLLOUT clock signal (clk_80m). I am trying to add an OFFSET delay (6.5ns) to the input signal, but I get the following warning (the constraint seems to be ignored):

[Warning message]
ConstraintSystem: 168-Constraint <NET "SAD15" OFFSET = IN 6.5ns VALID 12.5ns BEFORE "clk_80m" RISING;> [cube_top.ucf (656)]:
This constraint will be ignored because NET "clk_80m" could not be found or was not connected to a PAD.

According to the warning, it looks like the OFFSET delay can be applied to an external input clock, but not to an internally generated clock. So the question is, why can't the OFFSET delay be applied to a clock generated inside the chip? Is there an alternative solution?

Thank you for your help.
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Historian
Historian
138 Views
Registered: ‎01-23-2009

Re: ISE v14.7におけるOFFSET値の設定について

What would an OFFSET IN relative to an internal clock mean?

All constraints are meant to describe the timing characteristics of the system in which the FPGA is a part - it describes the timing of the stuff outside the FPGA. The static timing analysis in the tool then analyzes the timing to ensure that the FPGA will work with this external timing.

An OFFSET IN specifies the timing relationship between some clock reference and the input signal. Since the OFFSET IN is describing the timing relationship of something outside the FPGA, how can it be referenced to a clock that is inside the FPGA?

Because this is not a useful thing to do, there is no syntax for it. The "clk_name" for an OFFSET IN/OFFSET OUT is specifically defined as

clk_name defines the fully hierarchical name of the input clock pad net

(from UG625 in both the description of OFFSET IN and OFFSET OUT).

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