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Observer
Observer
13,736 Views
Registered: ‎03-12-2014

Identify a generated clock

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Hi,

 

One basic question: When I open a Synthesized design in Vivado, how do I come to know by reading the clock network report that which clock is PLL/MMCM generated and which clock is user generated? PLL/MMCM generated clocks are constrained by the tool itself, but I need to set constraints for the user generated clock. But how can I identify which clock is user generated? 

 

Thanks and regards,

Amitra

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Xilinx Employee
Xilinx Employee
22,658 Views
Registered: ‎02-16-2014

Re: Identify a generated clock

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Hi Amitra,

 

Clocks are generated when a primary clcok propagates to a cell that generates new clocks

  • MMCM,PLL,BUFR,HSSIO

User-derived clocks can be generated in the design using clock buffers.

  • BUFHCE,BUFGCE

 

In the report_clocks you have attached you can see that Master source for the user generated clock(clk_samp) is input of BUFHCE using which you are trying to generate a divide by 32 clock.

 

The remaining three clocks has the same Master source which is Input of MMCM.So they are MMCM generated clocks.

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Xilinx Employee
Xilinx Employee
13,732 Views
Registered: ‎02-16-2014

Re: Identify a generated clock

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Hi Amitra,

 

You can use report_clocks command for this info.

 

The output of this command will contain a Generated clocks section where it will show the details of all the generated clocks.

You can find the Master source for this generated clocksin that section.

 

Capture.PNG

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Moderator
Moderator
13,726 Views
Registered: ‎01-16-2013

Re: Identify a generated clock

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Observer
Observer
13,723 Views
Registered: ‎03-12-2014

Re: Identify a generated clock

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Hi Manisha,

 

I think that might be not the correct way to identify a user generated clock. Right now, I generated a clock by "Create Generated Clock" in "Timing Constraints" window of Vivado. I ran "report_clocks" and found the report below. All the clocks have a "Master Source" but only one is user generated (not PLL/MMCM generated). How can I identify which one is user generated from the report?

 

Clock Period Waveform Attributes Sources
clk_pin_p 5.00000 {0.00000 2.50000} P {clk_pin_p}
clkfbout_clk_core 5.00000 {0.00000 2.50000} P,G {clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKFBOUT}
clk_out1_clk_core 5.00000 {0.00000 2.50000} P,G {clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0}
clk_out2_clk_core 5.16129 {0.00000 2.58065} P,G {clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT1}
clk_samp 165.16130 {0.00000 82.58065} P,G {clk_gen_i0/BUFHCE_clk_samp_i0/O}


====================================================
Generated Clocks
====================================================

Generated Clock : clkfbout_clk_core
Master Source : clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKIN1
Master Clock : clk_pin_p
Multiply By : 1
Generated Sources : {clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKFBOUT}

 

Generated Clock : clk_out1_clk_core
Master Source : clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKIN1
Master Clock : clk_pin_p
Multiply By : 1
Generated Sources : {clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0}

 

Generated Clock : clk_out2_clk_core
Master Source : clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKIN1
Master Clock : clk_pin_p
Edges : {1 2 3}
Edge Shifts : {0.000 0.081 0.161}
Generated Sources : {clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT1}

 

Generated Clock : clk_samp
Master Source : clk_gen_i0/BUFHCE_clk_samp_i0/I
Master Clock : clk_out2_clk_core
Divide By : 32
Generated Sources : {clk_gen_i0/BUFHCE_clk_samp_i0/O}

 

Thanks and regards,

Amitra

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Moderator
Moderator
13,720 Views
Registered: ‎01-16-2013

Re: Identify a generated clock

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Hello,

 

When you create any clock and feed it to MMCM and PLL. The output generated by MMCM and PPL also know as generated clock but those are auto generated. 

When you overide any autogenaretd clock using generate_clock that is know as user generated clocks.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug903-vivado-using-constraints.pdf 

 

Thanks,

Yash

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Observer
Observer
13,699 Views
Registered: ‎03-12-2014

Re: Identify a generated clock

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Hi Yash,

 

Let me try to explain my question once more. I am following a Xilinx training on Clock Creation. Please find the attached snap as a screenshot of one slide of the training. In the hard copy of the training material, 'clk_samp' (clk_gen_i0/clk_samp) is marked as "User Generated Clock". While all other clocks (Like clk_out1_clk_core) is marked in the hardcopy as "MMCM/PLL generated clock". 

 

So, my question is how clk_samp was identified as User Generated while other clocks were identified as PLL/MMCM generated.

 

Thanks and regards,

Amitra

clock_network.jpg
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Xilinx Employee
Xilinx Employee
13,692 Views
Registered: ‎01-04-2013

Re: Identify a generated clock

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Hi Amitra,

 

Clock objects have properties that can be reported with the report_property command. Some of the properties on a clock object include IS_GENERATED and IS_USER_GENERATED. These will tell you if the clock is user generated. The following script should return the properties for all clocks in the design:

 

foreach x [get_clocks] {

   puts "Clock is $x"

   report_property -all $x

}

 

This command returns the user generated clocks:

 

get_clocks -filter {IS_USER_GENERATED}

 

Best regards,
Randy

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Moderator
Moderator
13,688 Views
Registered: ‎01-16-2013

Re: Identify a generated clock

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Hello Amitra,

 

So for user generated clock there is constraint you will find in XDC Create_generated_clock.

And for auto generated clock i.e. derived from MMCM/PLL you will not have any generated_clock constraints.

 

You can get complete list of generated clocks using get_generated_clocks command.

There is no specific command to distinguish between auto gnerated clocks and user generated clock.

 

Thanks,

Yash

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Xilinx Employee
Xilinx Employee
22,659 Views
Registered: ‎02-16-2014

Re: Identify a generated clock

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Hi Amitra,

 

Clocks are generated when a primary clcok propagates to a cell that generates new clocks

  • MMCM,PLL,BUFR,HSSIO

User-derived clocks can be generated in the design using clock buffers.

  • BUFHCE,BUFGCE

 

In the report_clocks you have attached you can see that Master source for the user generated clock(clk_samp) is input of BUFHCE using which you are trying to generate a divide by 32 clock.

 

The remaining three clocks has the same Master source which is Input of MMCM.So they are MMCM generated clocks.

View solution in original post

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Moderator
Moderator
13,685 Views
Registered: ‎01-16-2013

Re: Identify a generated clock

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I have never tried what Randy has suggested. But you can try that as well.

Thanks,
Yash
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Observer
Observer
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Registered: ‎03-12-2014

Re: Identify a generated clock

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Thanks to all for clearing the doubts. 

 

I will try Randy's script too.

 

Thanks and regards,

Amitra

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