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Explorer
Explorer
432 Views
Registered: ‎10-12-2016

In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi Friends, 

In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected".

 

What are the limitations ? 

Any help or suggestions are highly appreciated. 

Thank You 

S Sampath 

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1 Solution

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Moderator
Moderator
385 Views
Registered: ‎11-04-2010

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi, @ssampath ,

There is the routing resoruce to connect the BUFGs in the different halves.

The DRC of this connection can be overriden, but it is highly discouraged as it may lead to very poor timing results.

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi, @ssampath ,

There is 32 bufgs in 7 series device.

BUFGCTRL X0Y0~X0Y15 are in the bottom half of the decice and BUFGCTRL X0Y16~X0Y31 are in the top half.

The BUFGCTL in one half should not be used to drive the BUFGCTL in the other half of the device.

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Explorer
Explorer
410 Views
Registered: ‎10-12-2016

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi @hongh,

 

Can you please elaborate more, if possible just give small example theoritically(code is not required). 

Thank You

S Sampath

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Explorer
Explorer
408 Views
Registered: ‎10-12-2016

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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HI @hongh

But in the same user guide mentioned that, BUFG's can drive any clock pin in the device ?

Thank You 
S Sampath

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Moderator
Moderator
386 Views
Registered: ‎11-04-2010

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi, @ssampath ,

There is the routing resoruce to connect the BUFGs in the different halves.

The DRC of this connection can be overriden, but it is highly discouraged as it may lead to very poor timing results.

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Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Explorer
Explorer
381 Views
Registered: ‎10-12-2016

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi @hongh

 

In This what we have to do if i need other half BUFGCTRLs also  ?

 

Thank You 

S Sampath

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Moderator
Moderator
379 Views
Registered: ‎11-04-2010

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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Hi, @ssampath ,

You need to set the correct constraint and close timing, though sometimes it will be harder than the other situaions. 

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Historian
Historian
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Registered: ‎01-23-2009

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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@ssampath,

It is clear that you are going through the user guides and trying to make more sense of the clocking architecture of the 7 series devices - and this is a good thing.

However, I am not sure your approach is the best one. All the information on the clocking is in the User Guide, but it isn't necessarily presented in an order that allows you to understand everything in one pass. So trying to go through it once and asking questions on anything that isn't understood in the first pass isn't likely to get you a good picture.

It is possible to learn everything (or at least most things) by reading the User Guide, but you will have to be resigned to the fact that you won't understand everything on the first pass. My suggestion to you is that you

  • Start reading the User Guide
  • Everything that isn't immediately clear as you proceed, you should write down
    • Once you have taken note of it, move on
  • Many of your questions will be answered in another section a bit later
  • Some of the stuff won't make sense even after getting through the User Guide once
    • So start again - read through the guide a second time

At the end of this process, if you still have questions, ask them here.

But simply asking questions here first, may not get you "complete" (or even correct) answers - the questions are often too vague to really give proper answer to. Not all of the answers to this one are complete (or correct).

As an example, lets take this question. It is answered in the User Guide, but not in a single place.

So, you have gotten one important piece - any BUFG can drive the clock pin of any clockable cell (CLB flip-flop, IOB flip-flop, block RAM, distributed RAM, DSP cell, etc...), anywhere in the device. This is true regardless of the location of the clockable cell, as well as whether the BUFG is in the top half or the bottom half. The only limit is how many different BUFG domains can enter a clock region, which is capped at the number of BUFH per clock region (12).

The restrictions on top/bottom half have more to do with the inputs of the BUFG - what can drive the I (or I0 and I1) inputs of the BUFG/BUFGMUX/BUFGCTRL. Most of the restrictions are summarized in UG472 Table 1.1 - there it shows that the top/bottom restrictions for the BUFG are on the "Driven By" column, not on the "Drives" column.

The UG gets even more specific in the section on the BUFGCTRL; Chapter 2: Clocking Resources -> Global Clocking Resources -> Global Clock Buffers. Here it states:

  • CMTs in the top half of the device can only drive the BUFGs in the top half of the device
    and CMTs in bottom half can only drive BUFGs in the bottom half
  • only BUFGs
    in the same half of the device can be used as feedback to the CMTs in the same half of the
    device
  • The 7 series FPGAs clock-capable inputs can drive global clock buffers indirectly through
    the vertical clock network that exists in the clock backbone column. The 32 BUFGs are
    organized into two groups of 16 BUFGs in the top and bottom of the device. Any resources
    (for example, GTX transceivers) connecting to the BUFGs directly have a top/bottom
    limitation. For example, each MMCM in the top can only drive the 16 BUFGs residing in
    that top of the device. Similarly, the MMCMs in the bottom drive the 16 BUFGs in the
    bottom.
  • In the 7 series FPGAs clocking architecture BUFGCTRL multiplexers and all derivatives
    can be cascaded to adjacent clock buffers within the group of 16 in the upper and lower
    half of the device, effectively creating a ring of 16 BUFGMUXes (BUFGCTRL multiplexers)
    in the upper half and another ring of 16 in the lower half. Figure 2-2 shows a simplified
    diagram of cascading BUFGs.

So all the answers are there - they are just not all in the same place and in the introduction to the clocking resources.

Avrum

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Explorer
Explorer
346 Views
Registered: ‎10-12-2016

Re: In User guide 472 mentioned that "The top and bottom division separates two sets of global clock buffers and imposes some limitations on how they can be connected"

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@avrumw

 

Thank You, 

You are correct, It seems some sense to look overview once and come up with doubts. But with your answer i cleared some of my doubts. 

Thank You 

S Sampath

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