05-12-2017 07:36 AM
I am using Virtex 5 FPGA(Tool -Xilinx ISE) in my project. In Constraint guide it is written that
"For Virtex®-5 devices, the From To constraint controls both setup and hold paths."
So I want to know that how can I define Max Delay for Setup and Min Delay for Hold path?
If I have written following constraint in ucf file
TIMESPEC TS_FF2FF = FROM FFS TO FFS 10 ns;
Then What is Max Delay and Min Delay between two Flip Flops?
Please give me guidance for the same.
05-19-2017 01:47 PM
More importantly, you shouldn't!
Why would you want to do this?
The path from FF to FF is normally defined by the PERIOD constraint. When you define the PERIOD constraint, the tools understand the requirements for both the setup and hold check. These checks take more than just the PERIOD into account; they also budget for clock skew, jitter and (if necessary) duty cycle. The FROM TO constraint you applied does not account for some of these (i.e. jitter and duty cycle).
There are a few reasons to override the PERIOD checks with the FROM TO checks
- related asynchronous paths
- some paths around synchronizers
- mutlicycle paths
But these are special cases. For the first two, one tends to use the DATAPATH_ONLY flag, which disables hold checks (at least I am pretty sure it does). The last one (multicycle paths) uses a special format of the FROM TO where, instead of using a number for the delay value, you use an expression based on the TIMESPEC for the period constraint (i.e. TS_sys_clk * 2). In this case, the hold time remains a "normal" hold check, but the setup check is doubled.