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pulsar
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Explorer
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Registered: ‎04-16-2015

Incomplete Сonstraints Report

Hello all

I have made design that contain 2 clocks.
Definition in the constraint file :

# ADC_BIT_CLK_P Fbit = 280 MHz
create_clock -period 3.570 -name FMC_HPC_CLK0_M2C_P [get_ports FMC_HPC_CLK0_M2C_P]
set_input_jitter FMC_HPC_CLK0_M2C_P 0.010

# ADC_FRAME_CLK_P Fframe = 40 MHz
create_clock -period 25.000 -name FMC_HPC_CLK1_M2C_P [get_ports FMC_HPC_CLK1_M2C_P]
set_input_jitter FMC_HPC_CLK1_M2C_P 0.010

These are asynchronous clocks and their exact mutual positions in the timing diagram can not be defined.

In the design I use process with clock domain crossing.
This process is given below the post.

First time Implementaion gave critical warning:
"Timing constraint are not met"
for Inter Clock Path.

After that I added these lines into constraints.xdc:
set_max_delay 0.800 -datapath_only -from [get_pins Ch1_A_shift_0_reg/C] -to [get_pins {REG_ADC_1_reg[0]/D}]
............................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch1_A_shift_13_reg/C] -to [get_pins {REG_ADC_1_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch2_A_shift_0_reg/C] -to [get_pins {REG_ADC_2_reg[0]/D}]
............................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch2_A_shift_13_reg/C] -to [get_pins {REG_ADC_2_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch3_A_shift_0_reg/C] -to [get_pins {REG_ADC_3_reg[0]/D}]
............................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch3_A_shift_13_reg/C] -to [get_pins {REG_ADC_3_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch4_A_shift_0_reg/C] -to [get_pins {REG_ADC_4_reg[0]/D}]
............................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch4_A_shift_13_reg/C] -to [get_pins {REG_ADC_4_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch5_A_shift_0_reg/C] -to [get_pins {REG_ADC_5_reg[0]/D}]
..............................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch5_A_shift_13_reg/C] -to [get_pins {REG_ADC_5_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch6_A_shift_0_reg/C] -to [get_pins {REG_ADC_6_reg[0]/D}]
...........................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch6_A_shift_13_reg/C] -to [get_pins {REG_ADC_6_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch7_A_shift_0_reg/C] -to [get_pins {REG_ADC_7_reg[0]/D}]
...........................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch7_A_shift_13_reg/C] -to [get_pins {REG_ADC_7_reg[13]/D}]

set_max_delay 0.800 -datapath_only -from [get_pins Ch8_A_shift_0_reg/C] -to [get_pins {REG_ADC_8_reg[0]/D}]
.............................................................................................................
set_max_delay 0.800 -datapath_only -from [get_pins Ch8_A_shift_13_reg/C] -to [get_pins {REG_ADC_8_reg[13]/D}]


Synthesis and Implementation did not give any error and critical warning.

Then I did:
tools -> timing -> report clock interaction -> Report Timing...
and got the report:

From To Total Delay Requirement
---------------------------------------------------------------------------
Ch8_A_shift_1_reg/C REG_ADC_8_reg[1]/D 0.673 0.8
Ch2_A_shift_0_reg/C REG_ADC_8_reg[0]/D 0.583 0.8
Ch1_A_shift_7_reg/C REG_ADC_8_reg[7]/D 0.584 0.8
Ch7_A_shift_5_reg/C REG_ADC_8_reg[5]/D 0.584 0.8
Ch5_A_shift_3_reg/C REG_ADC_8_reg[3]/D 0.574 0.8
Ch6_A_shift_3_reg/C REG_ADC_8_reg[3]/D 0.576 0.8
Ch6_A_shift_2_reg/C REG_ADC_8_reg[2]/D 0.641 0.8
Ch8_A_shift_8_reg/C REG_ADC_8_reg[8]/D 0.643 0.8
Ch7_A_shift_13_reg/C REG_ADC_8_reg[13]/D 0.627 0.8
Ch3_A_shift_1_reg/C REG_ADC_8_reg[1]/D 0.542 0.8


But delay times for the most bits (out of 13) in 7 channels (out of absent in the report.
And delay times for all 13 bits of 4th channel absent in the report completely.

Please answer me on the questions:


1) Why times for most bits are missing from the report ?
2) How to find out the delay times for these bits ?


Thank you.
Best regards,
Viktor

--================== 1st channel ====================================================
process (ADC_BIT_CLK)
begin
if (ADC_BIT_CLK'event and ADC_BIT_CLK='1') then

Ch1_A_shift_13 <= Ch1_A_shift_11;
Ch1_A_shift_11 <= Ch1_A_shift_9;
Ch1_A_shift_9 <= Ch1_A_shift_7;
Ch1_A_shift_7 <= Ch1_A_shift_5;
Ch1_A_shift_5 <= Ch1_A_shift_3;
Ch1_A_shift_3 <= Ch1_A_shift_1;
Ch1_A_shift_1 <= Out_1A_DEL;
end if;
end process;

process (ADC_BIT_CLK)
begin
if (ADC_BIT_CLK'event and ADC_BIT_CLK='0') then

Ch1_A_shift_12 <= Ch1_A_shift_10;
Ch1_A_shift_10 <= Ch1_A_shift_8;
Ch1_A_shift_8 <= Ch1_A_shift_6;
Ch1_A_shift_6 <= Ch1_A_shift_4;
Ch1_A_shift_4 <= Ch1_A_shift_2;
Ch1_A_shift_2 <= Ch1_A_shift_0;
Ch1_A_shift_0 <= Out_1A_DEL;
end if;
end process;


-- for MSB First mode
process (ADC_FRAME_CLK)
begin
if (ADC_FRAME_CLK'event and ADC_FRAME_CLK='1') then
REG_ADC_1(13) <= Ch1_A_shift_13;
REG_ADC_1(12) <= Ch1_A_shift_12;
REG_ADC_1(11) <= Ch1_A_shift_11;
REG_ADC_1(10) <= Ch1_A_shift_10;
REG_ADC_1(9) <= Ch1_A_shift_9;
REG_ADC_1(8) <= Ch1_A_shift_8;
REG_ADC_1(7) <= Ch1_A_shift_7;
REG_ADC_1(6) <= Ch1_A_shift_6;
REG_ADC_1(5) <= Ch1_A_shift_5;
REG_ADC_1(4) <= Ch1_A_shift_4;
REG_ADC_1(3) <= Ch1_A_shift_3;
REG_ADC_1(2) <= Ch1_A_shift_2;
REG_ADC_1(1) <= Ch1_A_shift_1;
REG_ADC_1(0) <= Ch1_A_shift_0;
end if;
end process;


...........................................................................
.............. 2nd channel...7th channel .............................
...........................................................................


====================== 8th channel ============================
process (ADC_BIT_CLK)
begin
if (ADC_BIT_CLK'event and ADC_BIT_CLK='1') then

Ch8_A_shift_13 <= Ch8_A_shift_11;
Ch8_A_shift_11 <= Ch8_A_shift_9;
Ch8_A_shift_9 <= Ch8_A_shift_7;
Ch8_A_shift_7 <= Ch8_A_shift_5;
Ch8_A_shift_5 <= Ch8_A_shift_3;
Ch8_A_shift_3 <= Ch8_A_shift_1;
Ch8_A_shift_1 <= Out_8A;
end if;
end process;

process (ADC_BIT_CLK)
begin
if (ADC_BIT_CLK'event and ADC_BIT_CLK='0') then

Ch8_A_shift_12 <= Ch8_A_shift_10;
Ch8_A_shift_10 <= Ch8_A_shift_8;
Ch8_A_shift_8 <= Ch8_A_shift_6;
Ch8_A_shift_6 <= Ch8_A_shift_4;
Ch8_A_shift_4 <= Ch8_A_shift_2;
Ch8_A_shift_2 <= Ch8_A_shift_0;
Ch8_A_shift_0 <= Out_8A;
end if;
end process;

-- for MSB First mode
process (ADC_FRAME_CLK)
begin
if (ADC_FRAME_CLK'event and ADC_FRAME_CLK='1') then
REG_ADC_8(13) <= Ch8_A_shift_13;
REG_ADC_8(12) <= Ch8_A_shift_12;
REG_ADC_8(11) <= Ch8_A_shift_11;
REG_ADC_8(10) <= Ch8_A_shift_10;
REG_ADC_8(9) <= Ch8_A_shift_9;
REG_ADC_8(8) <= Ch8_A_shift_8;
REG_ADC_8(7) <= Ch8_A_shift_7;
REG_ADC_8(6) <= Ch8_A_shift_6;
REG_ADC_8(5) <= Ch8_A_shift_5;
REG_ADC_8(4) <= Ch8_A_shift_4;
REG_ADC_8(3) <= Ch8_A_shift_3;
REG_ADC_8(2) <= Ch8_A_shift_2;
REG_ADC_8(1) <= Ch8_A_shift_1;
REG_ADC_8(0) <= Ch8_A_shift_0;
end if;
end process;
--==============================================================

 

 

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