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hyleung
Adventurer
Adventurer
385 Views
Registered: ‎07-30-2013

Incorrect period reported in automatically derived clocks

Hi,

I have a clock generation block axi_clkgen_v1_0, in a Vivado block design.  The clkin period is set to 4 manually.  The Clk0 Div is set to 4.  I expect the clock period from this block is 16ns.  But the report_clocks shows the period of the output of the MMCM is 4:

Source clock to the clkgen block:

rx_div_clk 4.000 {0.000 2.000} P {i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK}

 

Derived clocks from the block:

mmcm_fb_clk_s 4.000 {0.000 2.000} P,G,A {i_system_wrapper/system_i/axi_adrv9009_rx_clkgen/inst/i_mmcm_drp/i_mmcme4/CLKFBOUT}
mmcm_clk_0_s 4.000 {0.000 2.000} P,G,A {i_system_wrapper/system_i/axi_adrv9009_rx_clkgen/inst/i_mmcm_drp/i_mmcme4/CLKOUT0}
mmcm_clk_1_s 6.000 {0.000 3.000} P,G,A {i_system_wrapper/system_i/axi_adrv9009_rx_clkgen/inst/i_mmcm_drp/i_mmcme4/CLKOUT1}
mmcm_clk_2_s 2.000 {0.000 1.000} P,G,A {i_system_wrapper/system_i/axi_adrv9009_rx_clkgen/inst/i_mmcm_drp/i_mmcme4/CLKOUT2}

 

Any comment or help to correct the period are welcome.

 

Thanks

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2 Replies
yashp
Moderator
Moderator
337 Views
Registered: ‎01-16-2013

Hi,
Looks like the IP configuration is not set correctly. Please revisit the output clock parameters.
Thanks,
Yash
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hyleung
Adventurer
Adventurer
319 Views
Registered: ‎07-30-2013

Hi Yash,

Thanks for your reply.  This is a design from ADI.  It happened that the rx_div_clk, supposedly a auto-derived clock from a mmcm, has forced by a create_clock of 4ns in one of the tcl file.  Because of this create_clock, Vivado has problem in propagate the delay down the clocking network.  I fixed it by a bandage solution: write another create_clock to the correct timing at the output of axi_clkgen_v1_0.

Thanks

Henry

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