UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer ssneed
Observer
307 Views
Registered: ‎02-20-2019

Input DDR timing constraint with clock wizard

Jump to solution

Hello.  I have a DDR input I am capturing with an IDDR primitive.  The DDR clock is routed through an IBUFG and then to an instance of a Clock Wizard.  The following constraints are applied, but the timing report lists the setup slack as -5.5 ns.  I plan on using the dynamic phase adjustment feature of the Clock Wizard module to meet my timing constraints, but I would like to set up the constraints and phase setting of the Clock Wizard so that I meet timing after implementation.

1) am I doing something wrong with my constraints that causes the -5.5ns slack?

2) is it possible to account for the delay of the Clock Wizard to eliminate this negative slack?

( I have manually set the Clock Wizard phase to 0 and to 90 degrees and have noticed no difference in the timing report)

-Sean

 

create_clock -period 5.880 -name DDRC_CLOCK -waveform {0.000 2.940} [get_ports fmc_ha_00_p]set ddr_clock_period 5.880
set dv_before_ddr_pos_edge 0.730
set dv_after_ddr_pos_edge 0.730
set dv_before_ddr_neg_edge 0.730
set dv_after_ddr_neg_edge 0.730

# CHA
set_input_delay -clock DDRC_CLOCK -max [expr $ddr_clock_period/2 - $dv_before_ddr_pos_edge] [get_ports fmc_ha_04_p]

set_input_delay -clock DDRC_CLOCK -min [expr $ddr_clock_period/2 - $dv_after_ddr_pos_edge] [get_ports fmc_ha_04_p]

set_input_delay -clock DDRC_CLOCK -clock_fall -max -add_delay [expr $ddr_clock_period/2 - $dv_before_ddr_neg_edge] [get_ports fmc_ha_04_p]

set_input_delay -clock DDRC_CLOCK -clock_fall -min -add_delay [expr $ddr_clock_period/2 - $dv_after_ddr_neg_edge] [get_ports fmc_ha_04_p]

 

DDR Timing Report.JPG
0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
278 Views
Registered: ‎05-14-2008

Re: Input DDR timing constraint with clock wizard

Jump to solution

It looks to me that the expressions you used to calculate the input delay values are not correct.

Which XDC template are you referring to?

Can you show us the timing diagram of the interface?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎05-14-2008

Re: Input DDR timing constraint with clock wizard

Jump to solution

It looks to me that the expressions you used to calculate the input delay values are not correct.

Which XDC template are you referring to?

Can you show us the timing diagram of the interface?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Observer ssneed
Observer
267 Views
Registered: ‎02-20-2019

Re: Input DDR timing constraint with clock wizard

Jump to solution

Hi Vivian,

I am attaching a picture of my input clocking network.  The DDR clock rising and falling edges are aligned mid-bit with the data.

I didn't use a template provided in Vivado.  I used one out of a Xilinx instructor led training manual.  I will try to locate a Vivado template and figure out what I am doing wrong.

-Sean

IDDR Input Timing.JPG
0 Kudos
Observer ssneed
Observer
259 Views
Registered: ‎02-20-2019

Re: Input DDR timing constraint with clock wizard

Jump to solution

I compared my constraints to the Center Aligned Double Data Rate XDC template and found my error.  The constraints I was using from the training manual I have were correct with respect to the template, I just copied them wrong.

Thanks for your help Vivian.

-Sean

0 Kudos