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Adventurer
Adventurer
12,089 Views
Registered: ‎09-02-2014

Input clock, "three clock regions" and output clock pins

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Hello,

 

I looked througn UG472 (7 Series FPGAs Clocking Resources), forum, other documents and didn't find answer for my questions:

 

1. As I understand, external clock should come at MRCC or SRCC pins (depends on local or global clock comes, and it's better to connect it with MRCC for more flexibility of board).

 

But in UG472 (page 29) said that "MRCCs function the same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access up to three clock regions."

 

Even Artix7 xc7a50 has 6 clock regions and Virtex 7 xc7v2000 has up to 22 clock regions. As I understand that phrase above,I can clock only 3 clock regoins by one external generator -- obviously, it is incorrect conclusion, but what does that phrase mean  in this case?

 

2. What pins should be used for output clock from FPGA?

For example, I want to modify clock from external generator and clock another FPGA or other device with it (up to 200 MHz if differetial clock). Is it a good way to use simple user I/O pins, or should be used some special pins, as MRCC/SRCC?

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Xilinx Employee
Xilinx Employee
23,554 Views
Registered: ‎05-07-2015

Re: Input clock, "three clock regions" and output clock pins

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HI @alexey123

 

1. As I understand that phrase above,I can clock only 3 clock regoins by one external generator -- obviously, it is incorrect conclusion, but what does that phrase mean  in this case?

 

The clock signal coming throuhg MRCC or SRCC, if connected to a BUFG(global buffer), can drive all the clock region i the FPGA. 
The 3 clock region driving capability of MRCC is that it can drive 3 clock regions (1 + 2 adjacent) without the need of a BUFG.

2. What pins should be used for output clock from FPGA?

You can use normal user I/O pins.  Please note that clock forwarding should be done  through a ODDR.
FYI : refer to use case 4 in this AR62488. which shows a schematic of clock forwarding topology and constraint writing for the same.

Thanks
Bharath
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3 Replies
Xilinx Employee
Xilinx Employee
23,555 Views
Registered: ‎05-07-2015

Re: Input clock, "three clock regions" and output clock pins

Jump to solution

HI @alexey123

 

1. As I understand that phrase above,I can clock only 3 clock regoins by one external generator -- obviously, it is incorrect conclusion, but what does that phrase mean  in this case?

 

The clock signal coming throuhg MRCC or SRCC, if connected to a BUFG(global buffer), can drive all the clock region i the FPGA. 
The 3 clock region driving capability of MRCC is that it can drive 3 clock regions (1 + 2 adjacent) without the need of a BUFG.

2. What pins should be used for output clock from FPGA?

You can use normal user I/O pins.  Please note that clock forwarding should be done  through a ODDR.
FYI : refer to use case 4 in this AR62488. which shows a schematic of clock forwarding topology and constraint writing for the same.

Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
Give Kudos to a post which you think is helpful.
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Adventurer
Adventurer
12,048 Views
Registered: ‎09-02-2014

Re: Input clock, "three clock regions" and output clock pins

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Thank you, @nagabhar

 

By the way, can you explain, what is the sense of avoiding a BUFG primitive? It helps to reach less value of delay or what? In which cases should I use strategy with three clock regoins instead of BUFG?

 

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Xilinx Employee
Xilinx Employee
12,043 Views
Registered: ‎05-07-2015

Re: Input clock, "three clock regions" and output clock pins

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HI @alexey123

 

If a clock is  going to resources in one  or two clock regions alone , then using a BUFR/BUFMR to drive that logic might result in alesser clock insertion delay.
One  other  common reason is that if  all the available BUFGs are  being used  already, A need for an additional clock input which drives only small amount of logic can be  met by placing it  on a BUFR/BUFMR (by  also restircting its load logic to the same/adjacent clock regions).
It is always better to use BUFG if one  is available for use.(as it gives more freedom for the tool to place and route large designs)

Thanks
Bharath
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