I have setup and hold violations in my design, I have written the timing constraints using the constraint wizard,
in my design I have a MMCM which has 3 output clocks which drives my whole design but I have Inter and Intra clock violations (setup and hold). I am worried about the inter clock violations on the same clock outputs. Can I make them false path? or should get the required constraints from the rtl team? if any dependencies are there.