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Participant
Participant
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Registered: ‎06-04-2020

Inter clock Setup and HOLD violations

Hello,

I have setup and hold violations in my design, I have written the timing constraints using the constraint wizard,

in my design I have a MMCM which has 3 output clocks which drives my whole design but I have Inter and Intra clock violations (setup and hold). I am worried about the inter clock violations on the same clock outputs. Can I make them false path? or should get the required constraints from the rtl team? if any dependencies are there.

 

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Moderator
Moderator
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Registered: ‎03-16-2017

@Harish_Algat ,

Always resolve your inter clock violations in the first place. It might be due to incorrectly handled clock domain crossing paths (without proper timing exceptions.)

Use report clock interaction to understand more about it. This blog will help you to resolve inter clock violations by adding proper timing exceptions. https://forums.xilinx.com/t5/Blog-Archive/How-to-Constrain-Clock-Interactions-correctly/td-p/794116

Once this will resolve, run implementation again, and observe the timing values after route. 

 

Regards,
hemangd

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