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Guide avrumw
Registered: ‎01-23-2009

Re: Interfacing Kintex 7 with FT232h

Mmm, say I have as inputs both a clock and a data bus. If I deskew the clock (so that some other output meets that clock in time) the input data and the clock are no longer in sync within_the_fpga_fabric. Could that happen?


They are still "in sync" - you are merely modifying the phase of the clock, hence changing the clock data phase relationship. This is exactly what you are trying to do in order to get an interface to meet timing.


Specifically, in the case of MMCM clock deskew, it is attempting to remove the effect of the large clock insertion latency that comes with driving a clock to all clocked elements in the FPGA...


Yes, it is possible to have contradictory (or at least complex) requirements on different interfaces associated with the same clock - you have to plan your clocking and I/O so that you can accomodate the needs of all the interface. The FPGAs give you lots of tools with which to do this (MMCMs with multiple outputs, IDELAY and ODELAY cells, IOB flip-flops/ISERDES/OSERDES) - it is up to you to put this all together to do what you need to do.


It is sort of looking like you might benefit from some more in-depth FPGA training. All the architectural features of the 7 series FPFGs are covered in the Xilinx Designing with the Xilinx 7 Series Families class.