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dschussheim
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Registered: ‎06-08-2017

Interfacing a Kintex-7 FPGA with a 2-channel DAC at 200 MHz with interleaved data lines

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Short version:

DAC chips have glitchy outputs, especially at max clock rate. What tests should I do, and what are good practices for interfacing with these chips?

Longer version:

I have a custom baseboard with multiple MAX5875 16-bit 2-channel 200 MSPS DACs. I'm using a Mercury+ KX2 FPGA module with a Kintex-7 FPGA.

I'm programming the DACs in interleaved mode, meaning the data for both channels is sent over the same 16 data lines. A 17th data line, select, determines which DAC channel receives the new data. Figure 4b in the data sheet shows the timing diagram for interleaved mode.

I'm seeing glitches on the DAC outputs when clocking at 200 MHz. I also see glitches at lower speed, possibly less frequent. The glitches seem to be short (of order the clock period), and random (i.e. it's not the same bit glitching each time).

As a sanity check I made a program that programs only 1 bit high at a time independently for both DAC channels. For example I can send 0010_0000_0000_0000 to the IDAC, and 0000_0010_0000_0000 to the QDAC. I scanned through all combinations, and did not see the output glitches that I see with an arbitrary output. To me, this test at least indicates that all the data lines are connected properly and are being set correctly by the FPGA, at least in a simple case.

I also tried sending a phase shifted 200MHz clock out to the DACs, in the hope that I could find a window that had no glitches, and was reproducible. This approach did not work either. I can find edges where the data-clock phase is definitely not good, but I couldn't find a phase that worked without any glitches.

I've also attached my modules for programming the DACs.

Could I get some feedback and advice for an approach to getting these chips working correctly? Are there any standard practices for programming this sort of DAC chip?

I'm happy to provide more information about the board or program. Thank you all for the assistance.

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dschussheim
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Registered: ‎06-08-2017

I know it's been a while, but I wanted to follow up on this post because I now have a better picture of where these glitches were from.

It seems that most of the issue was poor design of the digital GND plane on the circuit board. I designed it so that the FPGA and DACs had completely isolated GND planes; there was a cut between the FPGA plane and the local plane for each DAC. I've attached a picture. This meant that there wasn't a good path for the return current underneath the 200 MHz data lines. It seems that the return current found it's way back through the chips themselves, which led to glitches. With a new board with unbroken GND plane under the data lines, the glitches are mostly gone.

However I did still see some glitches on one of the DACs. This seems to be related to an impedance mismatch on the clock line. The clock is shared between 4 DACs and branches out from a central point. Adding a small resistance in series at the clock input on the DACs removes these glitches. The resistance I settled on is 33 ohms at each DAC CLK input. This value had margin above and below, meaning I don't see glitches if I go higher or lower in this resistance. It seems like this is considered an acceptable solution for LVCMOS data lines. Does anyone have any information or opinions on this? Or guesses about why I see glitches when the resistance is low?

Finally, having the correct timing constraints, which @avrumw patiently helped me understand also helps. Without the shifted output clock to the DACs, the timing is marginal, and sometimes glitches are apparent on a few of the DAC chips.

I'm not sure if it's considered OK to mark my own post as the solution, but I think I'll do that. This way summary is easily visible, and if a reader wants more information on how to properly clock and constrain chips like these, they can read the rest of the thread.

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avrumw
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Registered: ‎01-23-2009

First, what are your timing constraints? This interface looks simple if you just look at the timing diagram which shows tS and tH symmetrically around the rising edge of the clock. However, if you look at the datasheet numbers (which show tSETUP and tHOLD, which I assume to be the same) they are very NOT symmetrical; tSETUP=-0.6, tHOLD=2.1. This means the valid data must be there 0.6ns after the rising edge of the clock and remain until 2.1ns after the rising edge of the clock; which puts the valid window in the middle-ish of the high phase of the clock. This is not an ideal place for it.

To maximize the setup/hold margin, you will probably need to use two different clocks from the same MMCM - one to generate the data (and to run all your internal logic) and one to drive the ODDR that generates the forwarded. This assumes you are driving the DAC as a source synchronous device (forwarding the clock from the FPGA) rather than system synchronous (where the FPGA and DAC share a common clock input). This is a tough decision; the clock from the FPGA will have more jitter than a "clean" clock from an oscillator, and that jitter will translate into voltage error on the output of the DAC. Conversely trying to do 200MHz system synchronous interface with a 5ns period, of which the device use 1.5 will be very tough (maybe impossible without some external clock feedback). So show us your clock arrangement on the board.

Second, this is a parallel DAC, so you have 16 data bits changing every clock. You may need to keep an eye on the Simultaneously Switching Outputs; there are limits to how many I/O of a given bank can change simultaneously without experiencing VCCO droop and/or GND bounce. In some of the newer families (like Kintex-7) it is pretty hard to violate these requirements (the bank power and ground have been increased from previous generations), but there are still limits - particularly for LVCMOS outputs.

Avrum

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dschussheim
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I am having trouble posting to the forum for some reason. I posted my response in the attached PDF. Sorry about this.

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avrumw
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The constraints look reasonable - particularly if the fDACclkB is a positive shift with respect to the  non shifted clock that generates the data. I would generally confirm these with a look at both the setup and the hold detailed timing report just to be sure it is using the correct edges (but I think it should).

By "voltage error" do you mean that this will decrease the SNR?

Yes. This is a known feature of almost all DACs - clock jitter results in increased SNR.

How large of jitter can I expect from the FPGA generated clock? Is MMCM_TOUTJITTER the relevant spec here?

The jitter of the MMCM is part of it, but the clock will pick up more jitter as it travels through the clock tree (through a noisy digital environment), which will couple in more jitter before it reaches the pin. More jitter can be coupled in from noise on your VCCO power supply. While these can be significant, they will probably all be in a similar order to the MMCM jitter - so if 3x or so of the MMCM jitter isn't a problem, you are probably OK. Unfortunately it isn't possible (or at least easy) to get a numerical value for "how much jitter is there on an FPGA forwarded clock", which is why it is generally avoided for high precision analog design. For this reason, many DACs (but not, apparently this one) have a separate clock for the analog section and the digital data, with the assumption that the two clocks ultimately trace back to the same oscillator (they are mesochronous). The analog one usually comes straight from the oscillator (so is cleaner from a jitter point of view) the data one is forwarded through the sending device (the FPGA in this case). Unfortunately this requires a clock crossing in the DAC which increases latency (and adds uncertainty to the latency).

So show us your clock arrangement on the board.

Apologies, I'm not quite sure what you're looking for here. Do you want to see my board layout?

Knowing that it is clock forwarded is what I needed.

I am using LVCMOS33 for these signals. The board has 7 of these chips in total. The DACs use 41 lines in bank

So LVCMOS33 is one of the worst I/O standards for Simultaneously Switching Noise (Which is what Xilinx calls it - others call it SSO), and 41 is a HUGE number - I would be highly suspicious that this is your problem. You can get some information on this through the report_ssn command, but I haven't used it in a long time and I don't remember what kind of configuration it needs. But you should definitely look into this. Keeping all but one of the DACs idle (sending a constant value on both phases of the output) while testing only one would be a good way to reveal if this is the problem; if the corruption goes away when you do this it would be a likely culprit. You might also be able to see some of the corruption with a really good oscilloscope looking at the noise on both the VCCO and the output signals, although SSN is really corruption on the internal FPGA power grid (after the inductance of the balls and the internal routing).

This could also negatively affect the SNR of the DAC, since this will definitely manifest as jitter on the forwarded clock or clocks...

I thought of an an alternate way to send the data to the DACs

I didn't follow everything, but I don't think it would be better. If I understand what you are trying to do, the net result would be similar, with the exception that  you would be more sensitive to the duty cycle imbalance that is inherent in internal FPGA clocks. Also the constraints would probably have to change.

Avrum

avrumw
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Registered: ‎01-23-2009

Actually, the constraints are not right...

First, according to the datasheet of the MAX5875, the setup and hold are specified with respect to the rising edge of the clock, so there shouldn't be a "-clock_fall" in the constraints.

Second, the -max of a set_output_delay is the setup time, which is -0.6ns. The -min of a set_output_delay is the negative of the hold time, which is -2.1. So the correct constraints are

create_generated_clock -name fDACclkB -source [get_pins {UUT/ODDR_fDACclkB/C}] -divide_by 1 [get_ports {fDACclkB}]
set_output_delay -clock [get_clocks fDACclkB] -max -0.6 [get_ports {fDAC0_out[*]}] 
set_output_delay -clock [get_clocks fDACclkB] -min -2.1 [get_ports {fDAC0_out[*]}]
set_output_delay -clock [get_clocks fDACclkB] -max -0.6 [get_ports fDAC0_sel] 
set_output_delay -clock [get_clocks fDACclkB] -min -2.1 [get_ports fDAC0_sel]

[edit: the -max and -min were originally reversed]

Again, I would want to see the timing reports, but I suspect that this needs a set_multicycle_path 0 -setup on the output constraints

set_multicycle_path -setup 0 -to [get_ports {fDAC0_out[*] fDAC0_sel}]
set_multicycle_path -hold -1 -to [get_ports {fDAC0_out[*] fDAC0_sel}]

[Edit: I think the last line shouldn't be there - I would have to spend time figuring it out again...]

Avrum

dschussheim
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Registered: ‎06-08-2017

Thanks so much for your detailed replies. I apologize I haven't followed up with this sooner.

I think I need to have correct output constraints before more testing of SSO issues, right? I added in the set_output_delay constraints you wrote. I'd like to give you the timing reports, but I'm not sure how to get them for these signals specifically.... All I've been able to get is reports about signals within the FPGA. How can I get reports on specific output signals?

Could you give a bit more explanation on the set_multicycle_path constraints you wrote? set_multicycle_path 0 almost seems like a paradox to me.

 

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avrumw
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I'd like to give you the timing reports, but I'm not sure how to get them for these signals specifically..

In the Tcl console use the command

report_timing -to  [get_ports {fDAC0_out[*]}] 

This will give yo a text report. If you want to put it in the GUI for interactive operations

report_timing -to  [get_ports {fDAC0_out[*]}] -name fDAC0_out

Could you give a bit more explanation on the set_multicycle_path constraints you wrote? set_multicycle_path 0 almost seems like a paradox to me.

While the "set_multicycle_path" command is most often used for actual multicycle paths, it really modifies the default rules as to which clock edge captures a signal with respect to the clock edge that launched it. A normal path is captured on the clock after the one that launched it - this is the equivalent of set_multicycle_path 1

In a 2 cycle multicycle path, you want to change the relationship so that data launched at a given edge is captured not on the next clock edge, but the one after that - that is set_multicycle_path 2 - one more than a normal path.

In some cases on interfaces you want the data to capture the data on the same edge as the edge that launches the data; this is set_multicycle_path 0.

But for the first pass, do not use the set_multicycle_path command and let me see the complete timing path - from there we can look at how the interface needs to be modified.

As for looking at the SSOs, you probably do need a set_output_delay command on the outputs - just so that the tool understands which clock the output is related to. Even if the interface fails timing, you can still do the SSO analysis.

Avrum

dschussheim
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Here's the output into the Tcl console. It only outputs the path for fDAC0_out[12], I guess because its the shortest slack time? I attached the rest as well. This is without the set_multicycle_path constraints.

 

report_timing -to [get_ports {fDAC0_out[*]}]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Thu Jan 14 08:12:16 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}]
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             2.571ns  (required time - arrival time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in_1  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[12]
                            (output port clocked by fDACclkB  {rise@2.500ns fall@5.000ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Max at Slow Process Corner
  Requirement:            2.500ns  (fDACclkB rise@2.500ns - clk3_in_1 rise@0.000ns)
  Data Path Delay:        4.630ns  (logic 3.216ns (69.463%)  route 1.414ns (30.537%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -2.100ns
  Clock Path Skew:        2.792ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    10.083ns = ( 12.583 - 2.500 ) 
    Source Clock Delay      (SCD):    7.677ns
    Clock Pessimism Removal (CPR):    0.386ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in_1 rise edge)
                                                      0.000     0.000 r  
    AA4                                               0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clkINPUT0/clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     0.619 r  clkINPUT0/IBUF_inst/O
                         net (fo=1, routed)           1.605     2.224    clkINPUT0/clk_int
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.093     2.317 r  clkINPUT0/BUFG_inst/O
                         net (fo=33, routed)          1.747     4.064    sADC_fDAC/clk_out
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.077     4.141 r  sADC_fDAC/MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           2.114     6.255    sADC_fDAC/clk3_in
    BUFGCTRL_X0Y4        BUFG (Prop_bufg_I_O)         0.093     6.348 r  sADC_fDAC/BUFG_3/O
                         net (fo=119, routed)         1.329     7.677    fDAC_inst/FAST_DAC_0/clk3
    SLICE_X0Y157         FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X0Y157         FDRE (Prop_fdre_C_Q)         0.204     7.881 r  fDAC_inst/FAST_DAC_0/s_out_reg[12]/Q
                         net (fo=1, routed)           1.414     9.295    fDAC_inst/fDAC0_int[12]
    F20                  OBUF (Prop_obuf_I_O)         3.012    12.307 r  fDAC_inst/pins[12].OBUF_inst0/O
                         net (fo=0)                   0.000    12.307    fDAC0_out[12]
    F20                                                               r  fDAC0_out[12] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      2.500     2.500 f  
    AA4                                               0.000     2.500 f  clk (IN)
                         net (fo=0)                   0.000     2.500    clkINPUT0/clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     3.013 f  clkINPUT0/IBUF_inst/O
                         net (fo=1, routed)           1.497     4.510    clkINPUT0/clk_int
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.083     4.593 f  clkINPUT0/BUFG_inst/O
                         net (fo=33, routed)          1.589     6.182    sADC_fDAC/clk_out
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.073     6.255 f  sADC_fDAC/MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           1.991     8.246    sADC_fDAC/clk4_in
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.083     8.329 f  sADC_fDAC/BUFG_4/O
                         net (fo=2, routed)           1.251     9.580    fDAC_inst/clk4
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.318     9.898 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     9.898    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.685    12.583 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000    12.583    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism              0.386    12.969    
                         clock uncertainty           -0.192    12.778    
                         output delay                 2.100    14.878    
  -------------------------------------------------------------------
                         required time                         14.878    
                         arrival time                         -12.307    
  -------------------------------------------------------------------
                         slack                                  2.571    


 

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avrumw
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Sorry - I also need to see the hold time path

 

report_timing -to [get_ports {fDAC0_out[*]}] -hold

Avrum

 

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dschussheim
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Do you want it for all bits?

report_timing -to [get_ports {fDAC0_out[*]}] -hold
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Thu Jan 14 14:59:26 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}] -hold
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             1.273ns  (arrival time - required time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in_1  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[3]
                            (output port clocked by fDACclkB  {rise@2.500ns fall@5.000ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Min at Fast Process Corner
  Requirement:            -2.500ns  (fDACclkB rise@2.500ns - clk3_in_1 rise@5.000ns)
  Data Path Delay:        1.679ns  (logic 1.358ns (80.878%)  route 0.321ns (19.122%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -0.600ns
  Clock Path Skew:        2.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.756ns = ( 8.256 - 2.500 ) 
    Source Clock Delay      (SCD):    3.155ns = ( 8.155 - 5.000 ) 
    Clock Pessimism Removal (CPR):    0.487ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in_1 rise edge)
                                                      5.000     5.000 r  
    AA4                                               0.000     5.000 r  clk (IN)
                         net (fo=0)                   0.000     5.000    clkINPUT0/clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.126     5.126 r  clkINPUT0/IBUF_inst/O
                         net (fo=1, routed)           0.700     5.826    clkINPUT0/clk_int
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     5.852 r  clkINPUT0/BUFG_inst/O
                         net (fo=33, routed)          0.697     6.549    sADC_fDAC/clk_out
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     6.599 r  sADC_fDAC/MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           0.931     7.530    sADC_fDAC/clk3_in
    BUFGCTRL_X0Y4        BUFG (Prop_bufg_I_O)         0.026     7.556 r  sADC_fDAC/BUFG_3/O
                         net (fo=119, routed)         0.599     8.155    fDAC_inst/FAST_DAC_0/clk3
    SLICE_X0Y155         FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X0Y155         FDRE (Prop_fdre_C_Q)         0.100     8.255 r  fDAC_inst/FAST_DAC_0/s_out_reg[3]/Q
                         net (fo=1, routed)           0.321     8.576    fDAC_inst/fDAC0_int[3]
    K16                  OBUF (Prop_obuf_I_O)         1.258     9.834 r  fDAC_inst/pins[3].OBUF_inst0/O
                         net (fo=0)                   0.000     9.834    fDAC0_out[3]
    K16                                                               r  fDAC0_out[3] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      2.500     2.500 f  
    AA4                                               0.000     2.500 f  clk (IN)
                         net (fo=0)                   0.000     2.500    clkINPUT0/clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.292     2.792 f  clkINPUT0/IBUF_inst/O
                         net (fo=1, routed)           0.765     3.557    clkINPUT0/clk_int
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     3.587 f  clkINPUT0/BUFG_inst/O
                         net (fo=33, routed)          0.946     4.533    sADC_fDAC/clk_out
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.053     4.586 f  sADC_fDAC/MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           0.996     5.582    sADC_fDAC/clk4_in
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     5.612 f  sADC_fDAC/BUFG_4/O
                         net (fo=2, routed)           0.828     6.440    fDAC_inst/clk4
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.221     6.661 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     6.661    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         1.595     8.256 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000     8.256    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism             -0.487     7.769    
                         clock uncertainty            0.192     7.961    
                         output delay                 0.600     8.561    
  -------------------------------------------------------------------
                         required time                         -8.561    
                         arrival time                           9.834    
  -------------------------------------------------------------------
                         slack                                  1.273    


 

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avrumw
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Something doesn't look right...

First, it shows the edges of fDACclkB rising at 2.5 and falling at 5.0 - an inverted clock with respect to the internal clock. That shouldn't be the case unless you specifically asked for it. This can be done (and may even be the correct solution) by reversing the D1 and D2 of the ODDR driving forwarding the clock (connecting D1 to 0 and D2 to 1) and also changing the create_generated_clock command to use the -invert flag. But we didn't discuss that in the constraints, so I am wondering what's going on here.

But if that is the case (the ODDR is reversed and the -invert flag is used) the clock edges used look consistent; on a 5ns period, the setup requirement is 2.5ns and the hold requirement is -2.5ns - effectively the clock edge before the setup capture edge, which is consistent. So we need to figure out how the inverted clock got there.

But the overall timing doesn't make sense (and it's probably my fault) - if you add up all the uncertainties they are way more than one clock period. After looking at it a bit I realize I reversed the -min and -max flags in the constraints - the calculations were all correct; I determined that the setup was -0.6 which means the max is -0.6 and the hold is 2.1, which means the min is -2.1, but I reversed them in the command. As a cross check your max should never be smaller than your min. I will correct the constraints in my earlier reply.

The only other thing to note is the clock structure isn't optimal - normally the clock coming in (on a clock capable pin) should go directly to the MMCM, but you have a BUFG between the pin and the MMCM. This adds am unnecessary, significant and not PVT compensated delay to the clock path - this will have a negative impact on overall timing.

So fix all these things (the set_output_delays, the extra BUFG and investigate how the inversion got there) and then send both path reports again.

Avrum

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dschussheim
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Registered: ‎06-08-2017

I haven't been able to figure out the origin of the inversion yet. This is my output ODDR instantiation, from UG953:

 

 

ODDR #("OPPOSITE_EDGE", 1'b0, "SYNC")ODDR_fDACclkB(fDACclkB_int, clk_out, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0);
OBUF#(.DRIVE(12), .IOSTANDARD("LVCMOS33"), .SLEW("FAST"))OBUF_clkB(fDACclkB_out, fDACclkB_int);

 

 

That's not inverted, right? It should output 1 on the rising edge and 0 on the falling edge, I think. My constraints are as follows, no inversion:

 

create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]

create_generated_clock -name fDACclkB -source [get_pins {fDAC_inst/ODDR_fDACclkB/C}] -divide_by 1 [get_ports {fDACclkB}]
set_output_delay -clock [get_clocks fDACclkB] -max -0.6 [get_ports {fDAC0_out[*]}] 
set_output_delay -clock [get_clocks fDACclkB] -min -2.1 [get_ports {fDAC0_out[*]}]
set_output_delay -clock [get_clocks fDACclkB] -max -0.6 [get_ports fDAC0_sel] 
set_output_delay -clock [get_clocks fDACclkB] -min -2.1 [get_ports fDAC0_sel]

 

Thanks for fixing the max/min on the output_delay constraints. I fixed them on my end.

I removed the BUFG, but it looks like one gets inferred anyway?

 

report_timing -to  [get_ports {fDAC0_out[*]}]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Mon Jan 18 14:19:46 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}]
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.493ns  (required time - arrival time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in_1  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[2]
                            (output port clocked by fDACclkB  {rise@2.500ns fall@5.000ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Max at Slow Process Corner
  Requirement:            2.500ns  (fDACclkB rise@2.500ns - clk3_in_1 rise@0.000ns)
  Data Path Delay:        5.206ns  (logic 3.180ns (61.073%)  route 2.027ns (38.927%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -0.600ns
  Clock Path Skew:        2.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    10.083ns = ( 12.583 - 2.500 ) 
    Source Clock Delay      (SCD):    7.678ns
    Clock Pessimism Removal (CPR):    0.386ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in_1 rise edge)
                                                      0.000     0.000 r  
    AA4                                               0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     0.619 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.605     2.224    clk_IBUF
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.093     2.317 r  clk_IBUF_BUFG_inst/O
                         net (fo=33, routed)          1.747     4.064    sADC_fDAC/clk_in
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.077     4.141 r  sADC_fDAC/MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           2.114     6.255    sADC_fDAC/clk3_in
    BUFGCTRL_X0Y4        BUFG (Prop_bufg_I_O)         0.093     6.348 r  sADC_fDAC/BUFG_3/O
                         net (fo=119, routed)         1.330     7.678    fDAC_inst/FAST_DAC_0/clk3
    SLICE_X0Y155         FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X0Y155         FDRE (Prop_fdre_C_Q)         0.204     7.882 r  fDAC_inst/FAST_DAC_0/s_out_reg[2]/Q
                         net (fo=1, routed)           2.027     9.909    fDAC_inst/fDAC0_int[2]
    K17                  OBUF (Prop_obuf_I_O)         2.976    12.885 r  fDAC_inst/pins[2].OBUF_inst0/O
                         net (fo=0)                   0.000    12.885    fDAC0_out[2]
    K17                                                               r  fDAC0_out[2] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      2.500     2.500 f  
    AA4                                               0.000     2.500 f  clk (IN)
                         net (fo=0)                   0.000     2.500    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     3.013 f  clk_IBUF_inst/O
                         net (fo=1, routed)           1.497     4.510    clk_IBUF
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.083     4.593 f  clk_IBUF_BUFG_inst/O
                         net (fo=33, routed)          1.589     6.182    sADC_fDAC/clk_in
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.073     6.255 f  sADC_fDAC/MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           1.991     8.246    sADC_fDAC/clk4_in
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.083     8.329 f  sADC_fDAC/BUFG_4/O
                         net (fo=2, routed)           1.251     9.580    fDAC_inst/clk4
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.318     9.898 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     9.898    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.685    12.583 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000    12.583    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism              0.386    12.969    
                         clock uncertainty           -0.192    12.778    
                         output delay                 0.600    13.378    
  -------------------------------------------------------------------
                         required time                         13.378    
                         arrival time                         -12.885    
  -------------------------------------------------------------------
                         slack                                  0.493  

 

 

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avrumw
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I haven't been able to figure out the origin of the inversion yet. This is my output ODDR instantiation, from UG953:

You shouldn't instantiate module ports by position - you should always do it by name. Without looking at the library, I can't tell if the port order is correct. And it is certainly possible that the port order in some document is not what it actually is in the library.... 

But even if these ports are backwards, the tools can't figure out that this is an inverted clock - that would have to be described in the create_generated_clock command (with the -invert flag).

I presume there is no inversion on the clock path before the ODDR...

I removed the BUFG, but it looks like one gets inferred anyway?

The tools shouldn't (wouldn't) insert a buffer here - there must still be something in your code...

Finally, the output flip-flop s_out_reg is not packed into the IOB. For an output interface you should almost always use the IOB flip-flop. 

set_property IOB [get_ports fDAC0_out[*]]

And I need to see both the setup and the hold check reports...

Avrum

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dschussheim
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Registered: ‎06-08-2017

Thank you so much for all of your help so far. I really appreciate it.

OK so since there seemed to be a few problems here, I simplified stuff so that I just have: an input buffer for the clock, the MMCM instance, the fDAC modules, and a ramp signal to send the the two DAC channels (to prevent opt for optimizing everything away). Something in here fixed the BUFG issue and the inverted clock issue. Once we've got the timing constraints figured out for this simpler module, I'll add things back in and see where the problem is.

I fixed the port declarations so I'm using the .name(signal_name) format.

I added the IOB constraints:

 

 

set_property IOB        TRUE     [get_ports fDAC0_sel]
set_property IOB        TRUE     [get_ports fDAC0_out[*]]

 

 

With the new constraint on fDAC0_sel, I get the following warning and error in placement:

 

 

[Place 30-722] Terminal 'fDAC0_sel' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O

[Place 30-1008] Instance fDAC_inst/FAST_DAC_0/sel_int_reg has an inverted D pin which is unsupported in the Spartan 7, UltraScale and UltraScale+ architectures. 

 

 

I guess this is because I'm doing something funny in MAX5875.v? I've attached all the files for reference. I wasn't able to attach the xdc, but I could copy/paste into the reply if that will help. I didn't do that only because these posts are quite long already...

Anyway, with that constraint removed, implementation succeeds, but the design fails timing, specifically hold. Here's setup, then hold:

 

 

report_timing -to  [get_ports {fDAC0_out[*]}]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Tue Jan 19 12:16:27 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}]
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             5.181ns  (required time - arrival time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[1]
                            (output port clocked by fDACclkB  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Max at Slow Process Corner
  Requirement:            5.000ns  (fDACclkB rise@5.000ns - clk3_in rise@0.000ns)
  Data Path Delay:        3.293ns  (logic 3.293ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -0.600ns
  Clock Path Skew:        2.945ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.238ns = ( 12.238 - 5.000 ) 
    Source Clock Delay      (SCD):    4.752ns
    Clock Pessimism Removal (CPR):    0.459ns
  Clock Uncertainty:      0.072ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in rise edge)    0.000     0.000 r  
    AA4                                               0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     0.619 r  IBUF_inst/O
                         net (fo=1, routed)           1.081     1.700    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.077     1.777 r  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.436     3.213    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.093     3.306 r  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.446     4.752    fDAC_inst/FAST_DAC_0/CLK
    OLOGIC_X0Y160        FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[1]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y160        FDRE (Prop_fdre_C_Q)         0.366     5.118 r  fDAC_inst/FAST_DAC_0/s_out_reg[1]/Q
                         net (fo=1, routed)           0.000     5.118    fDAC_inst/fDAC0_int[1]
    J18                  OBUF (Prop_obuf_I_O)         2.927     8.045 r  fDAC_inst/pins[1].OBUF_inst0/O
                         net (fo=0)                   0.000     8.045    fDAC0_out[1]
    J18                                                               r  fDAC0_out[1] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      5.000     5.000 f  
    AA4                                               0.000     5.000 f  clk (IN)
                         net (fo=0)                   0.000     5.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     5.513 f  IBUF_inst/O
                         net (fo=1, routed)           0.986     6.499    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.073     6.572 f  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.329     7.901    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.083     7.984 f  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.251     9.235    fDAC_inst/CLK
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.318     9.553 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     9.553    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.685    12.238 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000    12.238    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism              0.459    12.697    
                         clock uncertainty           -0.072    12.626    
                         output delay                 0.600    13.226    
  -------------------------------------------------------------------
                         required time                         13.226    
                         arrival time                          -8.045    
  -------------------------------------------------------------------
                         slack                                  5.181    
report_timing -to  [get_ports {fDAC0_out[*]}] -hold
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Tue Jan 19 12:17:03 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}] -hold
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) :        -2.491ns  (arrival time - required time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[3]
                            (output port clocked by fDACclkB  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Min at Slow Process Corner
  Requirement:            0.000ns  (fDACclkB rise@0.000ns - clk3_in rise@0.000ns)
  Data Path Delay:        2.970ns  (logic 2.970ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -2.100ns
  Clock Path Skew:        3.361ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.057ns
    Source Clock Delay      (SCD):    4.237ns
    Clock Pessimism Removal (CPR):    0.459ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in rise edge)    0.000     0.000 r  
    AA4                                               0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     0.513 r  IBUF_inst/O
                         net (fo=1, routed)           0.986     1.499    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.073     1.572 r  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.329     2.901    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.083     2.984 r  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.253     4.237    fDAC_inst/FAST_DAC_0/CLK
    OLOGIC_X0Y156        FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[3]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y156        FDRE (Prop_fdre_C_Q)         0.338     4.575 r  fDAC_inst/FAST_DAC_0/s_out_reg[3]/Q
                         net (fo=1, routed)           0.000     4.575    fDAC_inst/fDAC0_int[3]
    K16                  OBUF (Prop_obuf_I_O)         2.632     7.207 r  fDAC_inst/pins[3].OBUF_inst0/O
                         net (fo=0)                   0.000     7.207    fDAC0_out[3]
    K16                                                               r  fDAC0_out[3] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      0.000     0.000 f  
    AA4                                               0.000     0.000 f  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     0.619 f  IBUF_inst/O
                         net (fo=1, routed)           1.081     1.700    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.077     1.777 f  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.436     3.213    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.093     3.306 f  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.443     4.749    fDAC_inst/CLK
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.366     5.115 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     5.115    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.942     8.057 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000     8.057    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism             -0.459     7.598    
                         output delay                 2.100     9.698    
  -------------------------------------------------------------------
                         required time                         -9.698    
                         arrival time                           7.207    
  -------------------------------------------------------------------
                         slack                                 -2.491    

 

 

 

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avrumw
Expert
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Registered: ‎01-23-2009

First for the warning.

To be packed into an IOB, a flip-flop's output must go only to the OBUF - either directly or through an IDELAY. No other connection is possible.

In your design the flip-flop sel_int_reg is both being driven out of the FPGA on the port "sel" and is also being used to drive the multiplexing of the s_out_reg inputs. This makes it impossible to be packed into the IOB. The fact that you renamed it (sel_int and sel) has no effect; there is still one flip-flop.

To fix this you will need to create two actual flip-flops - something like

always @(posedge clk) begin
   sel_int <= !sel_int;
   sel       <= !sel_int;
end

Now sel can be packed into the IOB and sel_int can be used for the MUXes.

However, the synthesis tool will view these two flip-flops as redundant and will remove one, so you need to put DONT_TOUCH on both of them

...
(* DONT_TOUCH = "TRUE" *) output reg sel,
...
(* DONT_TOUCH = "TRUE" *) reg sel_int;

(I may have the syntax a bit messed up - particularly for the output port, but the synthesis guide will give you the information you need).

Now for the timing. This looks correct. Yes, it is failing, but it makes sense

  • The setup is launched at the rising edge at time 0 and captured at the rising edge at time 5
  • The hold is launched at the rising edge at time 0 and captured at the rising edge at time 0

These are "normal" launch and capture edges - so you have cleaned up the inverted clock thing.

Next, it is telling you that the interface is possible - you have 5.181ns of positive slack on the setup check and -2.491ns of slack on the hold slack. Since the sum of these are positive, this means the interface is viable. Looked at another way, this is saying that if you can move the setup and hold capture edges (together) back (earlier) by somewhere between 2.491 and 5.181ns, this interface will pass both setup and hold.

The question is "how do you do that?".

The "simplest" way to "move" the edge on an SDR interface is to clock the capture on the falling edge instead of the rising. This has the net effect of moving the capture edges back 1/2 clock period - in your case 2.5ns. Unfortunately, this is not enough for your interface; the hold time will still be slightly negative. You need to move it "back" even more than 2.5ns. (I suspect, at some point in the past there was an attempt to capture on the falling edge and some portion of those constraints remained, resulting in the inverted clock - but it wasn't inverted the "right way"...)

So we need a different mechanism. The best one is to generate two clocks from your MMCM - one for generating the data outputs and one for generating the clock outputs. The "ideal" point for the clock would be 3.84ns earlier than the current capture point, which is at 5.00ns. This would decrease your setup margin by 3.84; 5.181-3.84=1.35ns of margin. It would increase your hold margin by 3.84; -2.491+3.84=1.35ns - creating the most margin for both setup and hold.

To do this, you would create a clock with a positive phase shift of 1.35ns, or 97.13degrees (1.35/5.00*360).

So have CLKOUT0 with a 0 degree phase shift and use this to drive the process to drive sel and s_out  (through a BUFG). Have CLKOUT1 have the same clock frequency but a phase shift of 97.13degrees (or as close as the clocking wizard can get) and have this drive the ODDR.

That should fix the timing. I think the edges will be correct; once you have this implemented you can check out the same two timing reports and see if they are correct.

Avrum

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dschussheim
Explorer
Explorer
1,206 Views
Registered: ‎06-08-2017

Looks like it did meet timing. I've included the setup and hold reports for fDAC0_out[*] and fDAC0_sel. The closest I could get the phase was 101.25 (45/4*9), MMCM (at least on my device) wants phases in multiples of 45/CLK_DIV.

So it looks like we're basically done with getting the timing constraints correct, at least on a single chip. I'm going to copy all this for the other 6 chips (there are 7 total), and see that if it passes timing. I'll check to see if they work at full speed without glitches, and also post the result of the ssn report.

Thanks again for all the help so far! Timing constraints and reports are finally beginning to make more sense to me.

 

report_timing -to  [get_ports {fDAC0_out[*]}]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Fri Jan 22 11:39:43 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}]
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             1.135ns  (required time - arrival time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[1]
                            (output port clocked by fDACclkB  {rise@1.328ns fall@3.828ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Max at Slow Process Corner
  Requirement:            1.328ns  (fDACclkB rise@1.328ns - clk3_in rise@0.000ns)
  Data Path Delay:        3.293ns  (logic 3.293ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -0.600ns
  Clock Path Skew:        2.691ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.238ns = ( 8.566 - 1.328 ) 
    Source Clock Delay      (SCD):    4.752ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in rise edge)    0.000     0.000 r  
    AA4                                               0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     0.619 r  IBUF_inst/O
                         net (fo=1, routed)           1.081     1.700    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.077     1.777 r  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.436     3.213    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.093     3.306 r  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.446     4.752    fDAC_inst/FAST_DAC_0/clk_in
    OLOGIC_X0Y160        FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[1]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y160        FDRE (Prop_fdre_C_Q)         0.366     5.118 r  fDAC_inst/FAST_DAC_0/s_out_reg[1]/Q
                         net (fo=1, routed)           0.000     5.118    fDAC_inst/fDAC0_int[1]
    J18                  OBUF (Prop_obuf_I_O)         2.927     8.045 r  fDAC_inst/pins[1].OBUF_inst0/O
                         net (fo=0)                   0.000     8.045    fDAC0_out[1]
    J18                                                               r  fDAC0_out[1] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      1.328     1.328 r  
    AA4                                               0.000     1.328 r  clk (IN)
                         net (fo=0)                   0.000     1.328    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     1.841 r  IBUF_inst/O
                         net (fo=1, routed)           0.986     2.827    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.073     2.900 r  MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           1.329     4.229    clk4_in
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.083     4.312 r  clk4_in_BUFG_inst/O
                         net (fo=1, routed)           1.251     5.563    fDAC_inst/clk_out
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.318     5.881 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     5.881    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.685     8.566 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000     8.566    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism              0.205     8.771    
                         clock uncertainty           -0.192     8.580    
                         output delay                 0.600     9.180    
  -------------------------------------------------------------------
                         required time                          9.180    
                         arrival time                          -8.045    
  -------------------------------------------------------------------
                         slack                                  1.135    




report_timing -to  [get_ports {fDAC0_out[*]}] -hold
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Fri Jan 22 11:39:51 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports {fDAC0_out[*]}] -hold
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.735ns  (arrival time - required time)
  Source:                 fDAC_inst/FAST_DAC_0/s_out_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk3_in  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_out[3]
                            (output port clocked by fDACclkB  {rise@1.328ns fall@3.828ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Min at Slow Process Corner
  Requirement:            -3.672ns  (fDACclkB rise@1.328ns - clk3_in rise@5.000ns)
  Data Path Delay:        2.970ns  (logic 2.970ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -2.100ns
  Clock Path Skew:        3.615ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.057ns = ( 9.385 - 1.328 ) 
    Source Clock Delay      (SCD):    4.237ns = ( 9.237 - 5.000 ) 
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in rise edge)    5.000     5.000 r  
    AA4                                               0.000     5.000 r  clk (IN)
                         net (fo=0)                   0.000     5.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     5.513 r  IBUF_inst/O
                         net (fo=1, routed)           0.986     6.499    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.073     6.572 r  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.329     7.901    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.083     7.984 r  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.253     9.237    fDAC_inst/FAST_DAC_0/clk_in
    OLOGIC_X0Y156        FDRE                                         r  fDAC_inst/FAST_DAC_0/s_out_reg[3]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y156        FDRE (Prop_fdre_C_Q)         0.338     9.575 r  fDAC_inst/FAST_DAC_0/s_out_reg[3]/Q
                         net (fo=1, routed)           0.000     9.575    fDAC_inst/fDAC0_int[3]
    K16                  OBUF (Prop_obuf_I_O)         2.632    12.207 r  fDAC_inst/pins[3].OBUF_inst0/O
                         net (fo=0)                   0.000    12.207    fDAC0_out[3]
    K16                                                               r  fDAC0_out[3] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      1.328     1.328 r  
    AA4                                               0.000     1.328 r  clk (IN)
                         net (fo=0)                   0.000     1.328    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     1.947 r  IBUF_inst/O
                         net (fo=1, routed)           1.081     3.028    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.077     3.105 r  MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           1.436     4.541    clk4_in
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.093     4.634 r  clk4_in_BUFG_inst/O
                         net (fo=1, routed)           1.443     6.077    fDAC_inst/clk_out
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.366     6.443 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     6.443    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.942     9.385 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000     9.385    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism             -0.205     9.180    
                         clock uncertainty            0.192     9.372    
                         output delay                 2.100    11.472    
  -------------------------------------------------------------------
                         required time                        -11.472    
                         arrival time                          12.207    
  -------------------------------------------------------------------
                         slack                                  0.735    

 

 

 

report_timing -to  [get_ports {fDAC0_sel}]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Fri Jan 22 11:42:01 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports fDAC0_sel]
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             1.121ns  (required time - arrival time)
  Source:                 fDAC_inst/FAST_DAC_0/sel_reg/C
                            (rising edge-triggered cell FDRE clocked by clk3_in  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_sel
                            (output port clocked by fDACclkB  {rise@1.328ns fall@3.828ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Max at Slow Process Corner
  Requirement:            1.328ns  (fDACclkB rise@1.328ns - clk3_in rise@0.000ns)
  Data Path Delay:        3.309ns  (logic 3.309ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -0.600ns
  Clock Path Skew:        2.694ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.238ns = ( 8.566 - 1.328 ) 
    Source Clock Delay      (SCD):    4.749ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in rise edge)    0.000     0.000 r  
    AA4                                               0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     0.619 r  IBUF_inst/O
                         net (fo=1, routed)           1.081     1.700    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.077     1.777 r  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.436     3.213    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.093     3.306 r  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.443     4.749    fDAC_inst/FAST_DAC_0/clk_in
    OLOGIC_X0Y165        FDRE                                         r  fDAC_inst/FAST_DAC_0/sel_reg/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y165        FDRE (Prop_fdre_C_Q)         0.366     5.115 r  fDAC_inst/FAST_DAC_0/sel_reg/Q
                         net (fo=1, routed)           0.000     5.115    fDAC_inst/fDAC0_sel_int
    E20                  OBUF (Prop_obuf_I_O)         2.943     8.059 r  fDAC_inst/OBUF_sel0/O
                         net (fo=0)                   0.000     8.059    fDAC0_sel
    E20                                                               r  fDAC0_sel (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      1.328     1.328 r  
    AA4                                               0.000     1.328 r  clk (IN)
                         net (fo=0)                   0.000     1.328    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     1.841 r  IBUF_inst/O
                         net (fo=1, routed)           0.986     2.827    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.073     2.900 r  MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           1.329     4.229    clk4_in
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.083     4.312 r  clk4_in_BUFG_inst/O
                         net (fo=1, routed)           1.251     5.563    fDAC_inst/clk_out
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.318     5.881 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     5.881    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.685     8.566 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000     8.566    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism              0.205     8.771    
                         clock uncertainty           -0.192     8.580    
                         output delay                 0.600     9.180    
  -------------------------------------------------------------------
                         required time                          9.180    
                         arrival time                          -8.059    
  -------------------------------------------------------------------
                         slack                                  1.121    




report_timing -to  [get_ports {fDAC0_sel}] -hold
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug  5 22:57:20 MDT 2020
| Date         : Fri Jan 22 11:42:12 2021
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports fDAC0_sel] -hold
| Design       : top
| Device       : 7k160t-ffg676
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.788ns  (arrival time - required time)
  Source:                 fDAC_inst/FAST_DAC_0/sel_reg/C
                            (rising edge-triggered cell FDRE clocked by clk3_in  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            fDAC0_sel
                            (output port clocked by fDACclkB  {rise@1.328ns fall@3.828ns period=5.000ns})
  Path Group:             fDACclkB
  Path Type:              Min at Slow Process Corner
  Requirement:            -3.672ns  (fDACclkB rise@1.328ns - clk3_in rise@5.000ns)
  Data Path Delay:        3.024ns  (logic 3.024ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           -2.100ns
  Clock Path Skew:        3.617ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.057ns = ( 9.385 - 1.328 ) 
    Source Clock Delay      (SCD):    4.235ns = ( 9.235 - 5.000 ) 
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.192ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.125ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk3_in rise edge)    5.000     5.000 r  
    AA4                                               0.000     5.000 r  clk (IN)
                         net (fo=0)                   0.000     5.000    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.513     5.513 r  IBUF_inst/O
                         net (fo=1, routed)           0.986     6.499    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.073     6.572 r  MMCME2_BASE_inst/CLKOUT3
                         net (fo=1, routed)           1.329     7.901    clk3_in
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.083     7.984 r  clk3_in_BUFG_inst/O
                         net (fo=18, routed)          1.251     9.235    fDAC_inst/FAST_DAC_0/clk_in
    OLOGIC_X0Y165        FDRE                                         r  fDAC_inst/FAST_DAC_0/sel_reg/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y165        FDRE (Prop_fdre_C_Q)         0.338     9.573 r  fDAC_inst/FAST_DAC_0/sel_reg/Q
                         net (fo=1, routed)           0.000     9.573    fDAC_inst/fDAC0_sel_int
    E20                  OBUF (Prop_obuf_I_O)         2.686    12.259 r  fDAC_inst/OBUF_sel0/O
                         net (fo=0)                   0.000    12.259    fDAC0_sel
    E20                                                               r  fDAC0_sel (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock fDACclkB rise edge)
                                                      1.328     1.328 r  
    AA4                                               0.000     1.328 r  clk (IN)
                         net (fo=0)                   0.000     1.328    clk
    AA4                  IBUF (Prop_ibuf_I_O)         0.619     1.947 r  IBUF_inst/O
                         net (fo=1, routed)           1.081     3.028    clkg
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT4)
                                                      0.077     3.105 r  MMCME2_BASE_inst/CLKOUT4
                         net (fo=1, routed)           1.436     4.541    clk4_in
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.093     4.634 r  clk4_in_BUFG_inst/O
                         net (fo=1, routed)           1.443     6.077    fDAC_inst/clk_out
    OLOGIC_X0Y166        ODDR (Prop_oddr_C_Q)         0.366     6.443 r  fDAC_inst/ODDR_fDACclkB/Q
                         net (fo=1, routed)           0.000     6.443    fDAC_inst/fDACclkB_int
    F19                  OBUF (Prop_obuf_I_O)         2.942     9.385 r  fDAC_inst/OBUF_clkB/O
                         net (fo=0)                   0.000     9.385    fDACclkB
    F19                                                               r  fDACclkB (OUT)
                         clock pessimism             -0.205     9.180    
                         clock uncertainty            0.192     9.372    
                         output delay                 2.100    11.472    
  -------------------------------------------------------------------
                         required time                        -11.472    
                         arrival time                          12.259    
  -------------------------------------------------------------------
                         slack                                  0.788    

 

 

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dschussheim
Explorer
Explorer
1,191 Views
Registered: ‎06-08-2017

One more question about the timing constraints: why are we using negative setup/hold values for the min/max?

 

set_output_delay -clock [get_clocks fDACclkB] -max -0.6 [get_ports {fDAC0_out[*]}] 
set_output_delay -clock [get_clocks fDACclkB] -min -2.1 [get_ports {fDAC0_out[*]}]
set_output_delay -clock [get_clocks fDACclkB] -max -0.6 [get_ports fDAC0_sel] 
set_output_delay -clock [get_clocks fDACclkB] -min -2.1 [get_ports fDAC0_sel]

 

Instead of positive?

 

set_output_delay -clock [get_clocks fDACclkB] -max 2.1 [get_ports {fDAC0_out[*]}] 
set_output_delay -clock [get_clocks fDACclkB] -min 0.6 [get_ports {fDAC0_out[*]}]
set_output_delay -clock [get_clocks fDACclkB] -max 2.1 [get_ports fDAC0_sel] 
set_output_delay -clock [get_clocks fDACclkB] -min 0.6 [get_ports fDAC0_sel]

 

I ask because a phase the DAC does not work with phase 101.25, but it does with -45, but of course then it violates timing.

I've also attached the ssn_report with all 7 DACs in the design. I don't get any failures, but I'm not sure what the margin percentage means. It also mentions FP_VTT_50 termination, but I don't have any termination, just a direct connection to the DAC inputs. Is the drive strength attribute or slew rate important here? Does the report tell us anything interesting.

One extra piece of information: I'm driving 3 of the DAC chips with one clock, and the other 4 chips with a second separate clock. That is, the clocks are in parallel with multiple chips. Is this bad practice, and could it be causing problems like I see? Say from reflections or something? I realize this question is maybe beyond the scope of this forum/post, but I want to give as much potentially relevant information as I can....

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avrumw
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Registered: ‎01-23-2009

One more question about the timing constraints: why are we using negative setup/hold values for the min/max?

Go back to my third post in this thread...

For a set_output_delay, the -max is the required setup time of the receiving device.

For a set_output_delay, the -min is the negative of the required hold time of the receiving device.

The datasheet states that the setup time is -0.6ns, therefore the -max is -0.6ns.

The datasheet states that the hold time is 2.1ns, therefore the -min is -2.1ns.

So the numbers look right... I can't explain the discrepancy between what you are seeing on the board and the timing numbers...

 I'm driving 3 of the DAC chips with one clock, and the other 4 chips with a second separate clock.

I'm not sure I'm following... Are you saying that you are using one output of the FPGA to drive the clock of more than one DAC? This wouldn't be a good idea... The whole point of source synchronous interfaces is that all the variability in the data timing is cancelled out by the same variability in the clock timing - this reduces the skew between the clock and the data at the receiver. If each FPGA data output is driving one pin of one DAC, but the clock forwarded from the FPGA is driving 3 or 4 DACs, then these are now unbalanced; there is a significantly higher load on the clock and much more routing. I'm not saying this won't work (since you should have lots of margin on this interface), but it definitely is not the way source synchronous is supposed to be done.

Avrum

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dschussheim
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Registered: ‎06-08-2017

I know it's been a while, but I wanted to follow up on this post because I now have a better picture of where these glitches were from.

It seems that most of the issue was poor design of the digital GND plane on the circuit board. I designed it so that the FPGA and DACs had completely isolated GND planes; there was a cut between the FPGA plane and the local plane for each DAC. I've attached a picture. This meant that there wasn't a good path for the return current underneath the 200 MHz data lines. It seems that the return current found it's way back through the chips themselves, which led to glitches. With a new board with unbroken GND plane under the data lines, the glitches are mostly gone.

However I did still see some glitches on one of the DACs. This seems to be related to an impedance mismatch on the clock line. The clock is shared between 4 DACs and branches out from a central point. Adding a small resistance in series at the clock input on the DACs removes these glitches. The resistance I settled on is 33 ohms at each DAC CLK input. This value had margin above and below, meaning I don't see glitches if I go higher or lower in this resistance. It seems like this is considered an acceptable solution for LVCMOS data lines. Does anyone have any information or opinions on this? Or guesses about why I see glitches when the resistance is low?

Finally, having the correct timing constraints, which @avrumw patiently helped me understand also helps. Without the shifted output clock to the DACs, the timing is marginal, and sometimes glitches are apparent on a few of the DAC chips.

I'm not sure if it's considered OK to mark my own post as the solution, but I think I'll do that. This way summary is easily visible, and if a reader wants more information on how to properly clock and constrain chips like these, they can read the rest of the thread.

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