Internal clock timing constraint in UCF

[meghtesad]

Hi ,

I have recently upgraded my ISE from 8.1 to 10.1 and I'm having trouble with a design that worked before.

I have the following lines in my UCF file:

NET "refclk_50mhz_bufg" TNM_NET = "refclk_50mhz_bufg";
TIMESPEC "TS_refclk_50mhz_bufg" = PERIOD "refclk_50mhz_bufg" 20.00 ns HIGH 50 %;

NET "refclk_100mhz_bufg" TNM_NET = "refclk_100mhz_bufg";
TIMESPEC "TS_refclk_100mhz_bufg" = PERIOD "refclk_100mhz_bufg" "TS_refclk_50mhz_bufg"/2 HIGH 50 %;

This used to work fine in ISE8.1i, but in 10.1i I get the following error:

ERROR:ConstraintSystem:59 - Constraint <NET
   "refclk_50mhz_bufg" TNM_NET = "refclk_50mhz_bufg";>
   [pm71_69_22_fpga_core.ucf(45)]: NET
   "refclk_50mhz_bufg" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

What has changed to cause this? How else can I define a timing constraint for an internal clock signal?

Thanks for your help.

[jared.chen]

What are you using to synthesis, XST or Synplify? You may look into the Technology Schematic View to check if refclk_50mhz_bufg exists in your design.

If you are using XST, please try to set the synthesis property "Keep Hierarchy" to "Soft/Yes".

[meghtesad]

I am using synplify pro.

In my HDL  I have:

  ATTRIBUTE syn_keep OF refclk_50mhz_bufg      : SIGNAL IS true;

and so on for all bufg clock signals.

[jared.chen]

Open the Synplify, then HDL-Analyst -> Technology -> Hierarchical View.

Can you find the refclk_50mhz_bufg from the Nets List?

[Anonymous]

I believe the net name has changed after synthesis, you have to find out the exact name of this net after BUFG.

You may also try this:

NET "*refclk_50mhz_bufg*" TNM_NET = refclk_50mhz_bufg_group;

Use the wildcard to avoid any mismatch.

[meghtesad]

I've realized that this is a problem with synplify_pro, which I am using for synthesis.

In certain situations, the new version of synplify is ignoring the "syn_keep" attribute that I have specified for those signals which I want to use in my timing constraints and so those signals are being optimized out. I have found a work-around for this issue to make sure the nets that I need are preserved through synthesis. 

Thanks for all your suggestions.

 Cheers.

[edwillys]

Sometimes the keep attribute doesn't work out correctly. At least with XST I usually get a conflict warning regarding the keep attribute.

[yakram]

Could you illustrate the way been used to make sure of signal preserving ?

Thanks :)

[ankury]

Hi

check this user guide http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/cgd.pdf (page 135,245) it describe about two attribute kEEP and SAVE.which preserve the signals