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Adventurer
Adventurer
1,281 Views
Registered: ‎05-12-2012

Is it possible to met timing?

Hi!

I try to connect high speed ADC to FPGA.

 

Given:

Data buses form ADC connected to Zynq-045 with -1 speed grade. Data pins are located in 3 adjanced banks (# 9, 10, 11).

Clock form ADC located in bank #10 MRCC.

 

Clocking scheme - source syncronous, clock frequency - 250 MHz, data mode - DDR.

Lets imagine that the data and clock traces are length matched.

 

By the ADC datasheet data and clock have time shift. Tsu = 575 ps, Thold = 1175 ps.

 

 

        _____________                    _____
______/               \________________/            
  ____________     ____________     __________
/              \ /              \ /                    
\______________/ \______________/ \___________
|575  |1175    | |575 |1175     |

 

 

I tried different schemes of clocking IDDR registers:

1) IBUFDS->BUFG

2) IBUFDS->BUFG->MMCM->BUFG

3) IBUFDS->MMCM->BUFG

4) IBUFDS->BUFMR->BUFIO

 

I tried different constraints methods (with virtual clock and whithout)

1) 

create_clock -period 4.000 -name bADCA_RDY_P [get_ports bADCA_RDY_P]

set_input_delay -clock [get_clocks bADCA_RDY_P] -min 1.175 [get_ports $adc_input_ports]
set_input_delay -clock [get_clocks bADCA_RDY_P] -max 1.575 [get_ports $adc_input_ports]
set_input_delay -clock [get_clocks bADCA_RDY_P] -clock_fall -min -add_delay 1.175 [get_ports $adc_input_ports]
set_input_delay -clock [get_clocks bADCA_RDY_P] -clock_fall -max -add_delay 1.575 [get_ports $adc_input_ports]

2) 

 

create_clock -period 4.000 -name bADCA_RDY_P [get_ports bADCA_RDY_P]
create_clock -period 4.000 -name adc_virt_clk

set_input_delay -clock adc_virt_clk -max -0.575 [get_ports $adc_input_ports]
set_input_delay -clock adc_virt_clk -min -0.825 [get_ports $adc_input_ports]
set_input_delay -clock adc_virt_clk -max -0.575 [get_ports $adc_input_ports] -clock_fall -add_delay
set_input_delay -clock adc_virt_clk -min -0.825 [get_ports $adc_input_ports] -clock_fall -add_delay

set_false_path -setup -rise_from [get_clocks adc_virt_clk] -fall_to [get_clocks bADCA_RDY_P]
set_false_path -setup -fall_from [get_clocks adc_virt_clk] -rise_to [get_clocks bADCA_RDY_P]
set_false_path -hold -rise_from [get_clocks adc_virt_clk] -rise_to [get_clocks bADCA_RDY_P]
set_false_path -hold -fall_from [get_clocks adc_virt_clk] -fall_to [get_clocks bADCA_RDY_P]

set_multicycle_path -setup -from [get_clocks adc_virt_clk] -to [get_clocks bADCA_RDY_P] 0
set_multicycle_path -hold -from [get_clocks adc_virt_clk] -to [get_clocks bADCA_RDY_P] -1

Really I hope, this methods are  have no big differeces (correct if I'm not right)

 

In result I get negative slacks in all cases.

I tried to use IDELAY on data inputs, but there is not effecitve, becouse if Setup slack are increased Hold slack are decreased and there is no point when both are positive.

 

I think that my valid data window are too small (Tvalid = 1750 ps) with actual clock period (Tclk = 4000 ps).

1) Am I rigth?

2) If so, what I should to do for correct receive ADC data?

 

 

 

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5 Replies
Highlighted
Historian
Historian
1,228 Views
Registered: ‎01-23-2009

Re: Is it possible to met timing?

So there is a minor error in your first constraints - the -max should be 1.425 (2.000 - 0.575), so there is a bit more margin in the interface. But other than that, the constraints look right.

 

But ultimately, 1.750ns may not be enough in this case. You have made this interface far worse than it could be since the pins are in multiple banks. The clocking scheme of CCIO->BUFR/BUFIO is a fair bit faster than any other one, but only if the pins are in the same bank - the use of the BUFMR makes the timing significantly worse. Even in a -1, it might have been possible to meet timing if they were in the same bank.

 

But what you have tried is pretty much what is available (with some minor modifications). If you are using the MMCM, then you get better timing adjustment by using the fine phase shift of the MMCM, rather than the IDELAY to change the clock/data relationship. But, if the sum of setup slack and hold slack is less than 0 with the MMCM (without the IDELAY), then this isn't enough to help.

 

You may get slightly better results using a PLL instead of an MMCM in option 3 (which will probably be the best bet in this case), and you might get even slightly better results by changing the bandwidth parameter of the MMCM/PLL, but these will only add a small amount of margin - you can try to see if it is enough. Of course the PLL doesn't do fine phase shift, so you will either need to use coarse phase shift or the IDELAY - the coarse phase shift may not give you enough precision and the IDELAY degrades timing.

 

Avrum

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Adventurer
Adventurer
1,143 Views
Registered: ‎05-12-2012

Re: Is it possible to met timing?

Thank you, @avrumw.

 

So there is a minor error in your first constraints - the -max should be 1.425 (2.000 - 0.575), so there is a bit more margin in the interface. But other than that, the constraints look right.

 Yes, it's my mistake.

 

If you are using the MMCM, then you get better timing adjustment by using the fine phase shift of the MMCM, rather than the IDELAY to change the clock/data relationship. But, if the sum of setup slack and hold slack is less than 0 with the MMCM (without the IDELAY), then this isn't enough to help.

I removed IDELAYs on data inputs, set BANDWIDTH property on MMCM to "LOW" and still have Setup+Slack < 0. 

 

Thus I assume, that I need dinamic calibration. And that's what I did.

I connect input clock (CLK) to IDDR, and capture it by generated clock CLK->MMCM->BUFG. In MMCM I use dynamic phase shift on feedback path, and adjust phase continuously whith a certain period of time, suchwise the number of zeros and ones on the IDDR/Q1 output becomes almost the same. I think that data and my generated clock (in CLK->IDDR/C capure point) in this case should be as on my shcheme above. But it's a bit complicated to calculate all possible variations in clock routings to many data IDDRs. Should I account it in my case?

 

0 Kudos
Adventurer
Adventurer
1,139 Views
Registered: ‎05-12-2012

Re: Is it possible to met timing?

Thank you, @avrumw.

 

So there is a minor error in your first constraints - the -max should be 1.425 (2.000 - 0.575), so there is a bit more margin in the interface. But other than that, the constraints look right.

 Yes, it's my mistake.

 

If you are using the MMCM, then you get better timing adjustment by using the fine phase shift of the MMCM, rather than the IDELAY to change the clock/data relationship. But, if the sum of setup slack and hold slack is less than 0 with the MMCM (without the IDELAY), then this isn't enough to help.

I removed IDELAYs on data inputs, set BANDWIDTH property on MMCM to "LOW" and still have Setup+Slack < 0. 

 

Thus I assume, that I need dinamic calibration. And that's what I did.

I connect input clock (CLK) to IDDR, and capture it by generated clock CLK->MMCM->BUFG. In MMCM I use dynamic phase shift on feedback path, and adjust phase continuously whith a certain period of time, suchwise the number of zeros and ones on the IDDR/Q1 output becomes almost the same. I think that data and my generated clock (in CLK->IDDR/C capure point) in this case should be as on my shcheme above. But it's a bit complicated to calculate all possible variations in clock routings to many data IDDRs. Should I account it in my case?

 

0 Kudos
Adventurer
Adventurer
1,151 Views
Registered: ‎05-12-2012

Re: Is it possible to met timing?

Thank you, @avrumw.

 

So there is a minor error in your first constraints - the -max should be 1.425 (2.000 - 0.575), so there is a bit more margin in the interface. But other than that, the constraints look right.

 Yes, it's my mistake.

 

If you are using the MMCM, then you get better timing adjustment by using the fine phase shift of the MMCM, rather than the IDELAY to change the clock/data relationship. But, if the sum of setup slack and hold slack is less than 0 with the MMCM (without the IDELAY), then this isn't enough to help.

I removed IDELAYs on data inputs, set BANDWIDTH property on MMCM to "LOW" and still have Setup+Slack < 0. 

 

Thus I assume, that I need dinamic calibration. And that's what I did.

I connect input clock (CLK) to IDDR, and capture it by generated clock CLK->MMCM->BUFG. In MMCM I use dynamic phase shift on feedback path, and adjust phase continuously whith a certain period of time, suchwise the number of zeros and ones on the IDDR/Q1 output becomes almost the same. I think that data and my generated clock (in CLK->IDDR/C capure point) in this case should be as on my shcheme above. But it's a bit complicated to calculate all possible variations in clock routings to many data IDDRs. Should I account it in my case?

 

0 Kudos
Adventurer
Adventurer
1,168 Views
Registered: ‎05-12-2012

Re: Is it possible to met timing?

Thank you, @avrumw.

 

So there is a minor error in your first constraints - the -max should be 1.425 (2.000 - 0.575), so there is a bit more margin in the interface. But other than that, the constraints look right.

 Yes, it's my mistake.

 

 

If you are using the MMCM, then you get better timing adjustment by using the fine phase shift of the MMCM, rather than the IDELAY to change the clock/data relationship. But, if the sum of setup slack and hold slack is less than 0 with the MMCM (without the IDELAY), then this isn't enough to help.

I removed IDELAYs on data inputs, set BANDWIDTH property on MMCM to "LOW" and still have Setup+Slack < 0. 

 

Thus I assume, that I need dynamic calibration. And that's what I did.

I connect input clock (CLK) to IDDR, and capture it by generated clock CLK->MMCM->BUFG. In MMCM I use dynamic phase shift on feedback path, and adjust phase continuously whith a certain period of time, suchwise the number of zeros and ones on the IDDR/Q1 output becomes almost the same. I think that data and my generated clock (in CLK->IDDR/C capure point) in this case should be as on my shcheme above. But it's a bit complicated to calculate all possible variations in clock routings to many data IDDRs and package routings to IOBs. Should I account it in my case and how?

 

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