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2,718 Views
Registered: ‎11-19-2013

Is there an advantage to constrant the frequency to be higher than the real frequency?

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hi,
if i want to enhance the reliability of the logic code, is it helpful to increase the constrant frequency of clock in ucf file ?
for example, the real global clock is 40mhz, the constrant of the clock frequency be set to 50mhz.
thanks, huang.
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Moderator
Moderator
4,682 Views
Registered: ‎07-01-2015

Hi huangj852010@163.com,

 

You can see maximum frequency met by the design in .twr file.

ISE timing tools are pessimistic, so ideally there is no need for increasing clock frequency.

In case you still want to over constrain the design, please go for adding system jitter. 

Thanks,
Arpan
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Moderator
Moderator
2,716 Views
Registered: ‎11-09-2015

Hi huangj852010@163.com,

 

I don't think there is really an advantage in over-constraining a clock. If the design is passing timing then the design shouldn't fail in HW.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
2,707 Views
Registered: ‎11-04-2010

Hi huangj852010@163.com,
ISE timing tool has considered the most pessimistic situation if your constraint is correctly set.
No need to overconstrain the design for the purpose of reliability.

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Highlighted
Moderator
Moderator
4,683 Views
Registered: ‎07-01-2015

Hi huangj852010@163.com,

 

You can see maximum frequency met by the design in .twr file.

ISE timing tools are pessimistic, so ideally there is no need for increasing clock frequency.

In case you still want to over constrain the design, please go for adding system jitter. 

Thanks,
Arpan
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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Highlighted
2,652 Views
Registered: ‎11-19-2013
Thank you all for help, but could you tell me how to add the system jitter?
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Moderator
Moderator
2,649 Views
Registered: ‎07-01-2015

Hi huangj852010@163.com,

 

Please go through page-269 and 270 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgd.pdf for syntax of system jitter.

Thanks,
Arpan
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