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Explorer
Explorer
3,051 Views
Registered: ‎07-29-2009

JESD204 relationship between sysref and refclk

I have one last timing failure in the design, which I don't think I've constrained right. I am using the JESD using the "include shared logic in core" option. I have the refclk_n and p coming directly from a pin into the core. On the other hand, the sysref is a differential input signal so I am using an IBUFDS in to a BUFG into the core.

I get the following timing violation (in the picture).  I know the JESD204 7.1 PG066 says the constraint for sysref is a max and min input delay, but it seems to be considering the sysref as a clk so I cannot use that constraint, I think. Can you tell me what I'm doing wrong and how I'd properly fix this violation?

 

timingconstraintrefclk.PNG

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8 Replies
Observer mowerj
Observer
1,650 Views
Registered: ‎12-28-2014

Re: JESD204 relationship between sysref and refclk

Do you have any follow up to this question? I have a design and as the resource usage has increased on chip, I find that no matter what, I get a timing error between the ibufds and sysref.
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Explorer
Explorer
1,638 Views
Registered: ‎07-29-2009

Re: JESD204 relationship between sysref and refclk

No, no one responded.

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Moderator
Moderator
1,600 Views
Registered: ‎01-16-2013

Re: JESD204 relationship between sysref and refclk

Hi,

Apologies for delayed response.

I can see the source clock and destination clock periods are different. And from the report looks like this path you are trying to analyze under max delay of 0.5ns.

Why you are trying to give such higher requirements?
This two clock have 20ns period and 6.4ns period, is both clock coming from same source? If not do you have any CDC circuite to handle this clock domain crossing?

I feel this is case of over constraining the design rather than true failure. If you can provide more details it will be helpful for me to provide further suggestion.

Thanks,
Yash
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Explorer
Explorer
1,592 Views
Registered: ‎07-29-2009

Re: JESD204 relationship between sysref and refclk

I honestly have no idea where it is getting the 0.5 ns constraint.  I assumed it was built into the JESD core's constraints.  Here are mine, and I do not see anything related to 0.5 ns:

 

create_clock -period 6.400 -name refclk_p -waveform {0.000 3.200} [get_ports refclk_p]
create_clock -period 20.000 -name SYSREF_IN_D -waveform {0.000 10.000} [get_ports CLK_IN_SYSREF_clk_p]
create_clock -period 10000.000 -name onepps -waveform {0.000 5000.000} [get_ports onepps]
set_false_path -from [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinclo_reg*] -to [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinchi_reg*]
set_false_path -from [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseoffsetlo_reg*] -to [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseoffsethi_reg*]
set_false_path -from [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/reset_nlo_reg*] -to [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/reset_hi_reg[0]}]
set_false_path -from [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/chipratelo_reg*}] -to [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/chipratehi0_reg*}]
set_false_path -from [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/lfsr_gen/seqindexReglo_reg*}] -to [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/lfsr_gen/seqindexReghi_reg*}]
set_false_path -from [get_cells reference_emitter_i/verandfreqcount_0/inst/verandfreqcount_v1_0_S00_AXI_inst/clckcrosserhi_reg*] -to [get_cells reference_emitter_i/verandfreqcount_0/inst/verandfreqcount_v1_0_S00_AXI_inst/tempewma_reg*]
set_max_delay -datapath_only -from [get_ports onepps] -to [get_cells reference_emitter_i/verandfreqcount_0/inst/verandfreqcount_v1_0_S00_AXI_inst/statehmeta_reg] 6.400
set_max_delay -datapath_only -from [get_ports CLK_IN_SYSREF_clk_p] -to [get_cells reference_emitter_i/jesd204_0/inst/jesd204_block_i/tx_sysref_r_reg] 3.200
set_max_delay -datapath_only -from [get_ports onepps] -to [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/statemeta_reg] 6.400
set_max_delay -datapath_only -from [get_cells reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/reset_nlo_reg*] -to [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/U1/reset_hi_reg[0]}] 3.200
set_max_delay -datapath_only -from [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/event_toggle_reg*}] -to [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/signal_meta_reg*}] 3.200
set_max_delay -datapath_only -from [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/lfsr_gen/event_toggle_reg*}] -to [get_cells {reference_emitter_i/siggen_jesd_axi_0/inst/siggen_jesd_axi_v1_0_S00_AXI_inst/modulation[*].mod_lfsr_refem/lfsr_gen/signal_meta_reg*}] 3.200
set_false_path -from [get_cells -hier -filter {name =~ *jesd204_block_i/tx_cfg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *jesd204_block_i/tx_sysref_delay_reg* && IS_SEQUENTIAL}]
set_multicycle_path -setup -from [get_cells -hier -filter {name =~ *jesd204_block_i/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *IP2Bus_Data_reg* && IS_SEQUENTIAL}] 3
set_multicycle_path -hold -from [get_cells -hier -filter {name =~ *jesd204_block_i/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *IP2Bus_Data_reg* && IS_SEQUENTIAL}] 2
set_multicycle_path -setup -from [get_cells -hier -filter {name =~ *jesd204_block_i/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/GEN_USE_WSTRB.bus2ip_be_reg_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *IP2Bus_Data_reg* && IS_SEQUENTIAL}] 3
set_multicycle_path -hold -from [get_cells -hier -filter {name =~ *jesd204_block_i/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/GEN_USE_WSTRB.bus2ip_be_reg_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *IP2Bus_Data_reg* && IS_SEQUENTIAL}] 2
set_multicycle_path -setup -from [get_cells -hier -filter {name =~ *jesd204_block_i/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].rdce_out_i_reg[0] && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *IP2Bus_Data_reg* && IS_SEQUENTIAL}] 3
set_multicycle_path -hold -from [get_cells -hier -filter {name =~ *jesd204_block_i/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].rdce_out_i_reg[0] && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *IP2Bus_Data_reg* && IS_SEQUENTIAL}] 2

 

Tags (1)
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Explorer
Explorer
1,570 Views
Registered: ‎07-29-2009

Re: JESD204 relationship between sysref and refclk

Actually, I think this goes away during implementation, but exists in the synthesis report. I don't know why either occurs.

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Moderator
Moderator
1,558 Views
Registered: ‎01-16-2013

Re: JESD204 relationship between sysref and refclk

Hi,

As you mentioned this looks like at synthesis can you please check the JESD IP OOC constraints file??

In post-implemented design if you report out the timing report for same path what requirement it showing?

Thanks,
Yash

Thanks,
Yash
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Explorer
Explorer
1,548 Views
Registered: ‎07-29-2009

Re: JESD204 relationship between sysref and refclk

Instead of me looking everywhere for it, do you have a quick tip on where I could find those specifically?

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Moderator
Moderator
1,514 Views
Registered: ‎01-16-2013

Re: JESD204 relationship between sysref and refclk

Hi @petersk,

As there is difference in timing requirement at two stages, you need to cross verify those at OOC constraint file and post-implemented results.

Thanks,
Yash
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