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Contributor
Contributor
643 Views
Registered: ‎06-20-2018

JESD204B Timing Violation from Sync and Sysref

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Hello

 

I have a design to interface between Xilinx ZCU102 and ADI AD9162 Board.

 

I have completed the block design, which is shown below. The design could pass timing when the JESD204B core is clocked at fclk = 100 MHz. When I increases it to full JESD204B rate (fclk = 312.5 MHz), Vivado suggests 2 setup and holding timing violations from sysref and sync signal paths.

 

Is there any suggestion on how to clear this errors? Below are my constraint settings. What else do I need to add in my constraints?

 

Thank you

 

 

# RESET
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports tx_reset]

# clock speed
create_clock -period 3.200 -name refclk_pad_p [get_ports refclk_pad_p]
create_clock -period 40.000 -name spi_clk [get_ports spi_clk]

# FMC_HPC 0
set_property -dict {PACKAGE_PIN G8} [get_ports refclk_pad_p]
set_property -dict {PACKAGE_PIN G7} [get_ports refclk_pad_n]

set_property IOSTANDARD LVDS [get_ports {sync_in_clk_n[0]}]
set_property IOSTANDARD LVDS [get_ports {sync_in_clk_p[0]}]
set_property PACKAGE_PIN V2 [get_ports {sysref_in_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {sysref_in_clk_n[0]}]
set_property IOSTANDARD LVDS [get_ports {sysref_in_clk_p[0]}]
set_property PACKAGE_PIN AB4 [get_ports {sync_in_clk_p[0]}]
set_property PACKAGE_PIN G4 [get_ports {txp_out[0]}]
set_property PACKAGE_PIN H6 [get_ports {txp_out[1]}]

# SPI constraints
set_property IOSTANDARD LVCMOS18 [get_ports spi_miso]
set_property PACKAGE_PIN AA2 [get_ports spi_miso]
set_property IOSTANDARD LVCMOS18 [get_ports spi_mosi]
set_property PACKAGE_PIN Y1 [get_ports spi_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports cs0n]
set_property PACKAGE_PIN AA1 [get_ports cs0n]
set_property IOSTANDARD LVCMOS18 [get_ports cs1n]
set_property PACKAGE_PIN AB3 [get_ports cs1n]
set_property IOSTANDARD LVCMOS18 [get_ports cs2n]
set_property PACKAGE_PIN W2 [get_ports cs2n]
set_property PACKAGE_PIN Y2 [get_ports spi_clk]
set_property IOSTANDARD LVCMOS18 [get_ports spi_clk]
set_property IOSTANDARD LVCMOS18 [get_ports {fmc_spi_enb[0]}]
set_property PACKAGE_PIN AC3 [get_ports {fmc_spi_enb[0]}]
set_property PACKAGE_PIN J15 [get_ports spi_debug]
set_property IOSTANDARD LVCMOS33 [get_ports spi_debug]

1.jpg 

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Contributor
Contributor
639 Views
Registered: ‎06-20-2018

Re: JESD204B Timing Violation from Sync and Sysref

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This problem was resolved with these constraints

 

 

# timing constraints to sync and sysref
set_max_delay -datapath_only -from [get_ports sysref_in_*] -to [get_pins JESD_Simple_i/JESD_SubSys/jesd204_0/inst/tx_sysref_r_reg/D] 2.000
set_max_delay -datapath_only -from [get_ports sync_in_*] -to [get_pins JESD_Simple_i/JESD_SubSys/jesd204_0/inst/i_JESD_Simple_jesd204_0_0/i_tx/sync_r_reg/D] 2.000

 

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Highlighted
Contributor
Contributor
640 Views
Registered: ‎06-20-2018

Re: JESD204B Timing Violation from Sync and Sysref

Jump to solution

This problem was resolved with these constraints

 

 

# timing constraints to sync and sysref
set_max_delay -datapath_only -from [get_ports sysref_in_*] -to [get_pins JESD_Simple_i/JESD_SubSys/jesd204_0/inst/tx_sysref_r_reg/D] 2.000
set_max_delay -datapath_only -from [get_ports sync_in_*] -to [get_pins JESD_Simple_i/JESD_SubSys/jesd204_0/inst/i_JESD_Simple_jesd204_0_0/i_tx/sync_r_reg/D] 2.000

 

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