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2,919 Views
Registered: ‎01-22-2015

LVDS I/O constraints

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FPGA I/O (1-bit) via LVDS requires use of specially designated pin-pairs on the FPGA.  These LVDS pin-pairs have a P-side and an N-side.  However, for LVDS I/O, we write a constraint (eg. set_input_delay, set_output_delay) only for the P-side of the pin-pair. 

 

What assumptions are we making by not writing a constraint for the N-side of the pin-pair?  Other cautions?

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Voyager
Voyager
5,038 Views
Registered: ‎06-24-2013

Re: LVDS I/O constraints

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Hey markg@prosensing.com,

 

What assumptions are we making by not writing a constraint for the N-side of the pin-pair?

I think the basic assumptions are:

  • The N-side uses the same I/O Standard/Drive/Slew/etc as the P-side
  • The pair is matched properly (routed with identical length)

Best,

Herbert

-------------- Yes, I do this for fun!

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4 Replies
Voyager
Voyager
5,039 Views
Registered: ‎06-24-2013

Re: LVDS I/O constraints

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Hey markg@prosensing.com,

 

What assumptions are we making by not writing a constraint for the N-side of the pin-pair?

I think the basic assumptions are:

  • The N-side uses the same I/O Standard/Drive/Slew/etc as the P-side
  • The pair is matched properly (routed with identical length)

Best,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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Guide avrumw
Guide
2,860 Views
Registered: ‎01-23-2009

Re: LVDS I/O constraints

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A P/N pair of a differential signal is really a single signal - it is just carried over a pair of wires and pins. The signal should have only one timing constraint, which should be applied to the P pin - you should never put timing constraints on the N pin.

 

For the physical constraints, the tools assume that if the P side is configured with a particular differential standard (and associated properties) the N side will be the same. However, in this case, it is legal (but not necessary) to apply the properties to both the N and P.

 

Avrum

2,851 Views
Registered: ‎01-22-2015

Re: LVDS I/O constraints

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Herbert - thanks!  My Googling found articles describing proper design of LVDS traces on a circuit board.  -and, if followed, will result in the assumed-conditions you have listed.

 

Avrum - thanks for clarifying the needed timing constraints ... and for the reminder about the needed physical constraints!

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Voyager
Voyager
2,848 Views
Registered: ‎06-24-2013

Re: LVDS I/O constraints

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markg@prosensing.com,

 

You're welcome!

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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