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Contributor
Contributor
507 Views
Registered: ‎11-10-2017

Large Hold time violation in AXI Interconnect

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Hello.

I am developing some HLS IP.

When I add my HLS IP on Vivado and run synthesis, Large Hold time violation is appeared in AXI Interconnect, not in my HLS IP.

What should I do? Can I solve this large violation in easy way?

In my HLS IP, I use 2 functions. When I high-level synthesized only either function, Timing violation is not appeared. (I have tried both function.)

So I think this timing violation is caused by my huge resource utilization.

I also tried to split my HLS IP to two HLS IP, and connect them to PS and use different clock from PS, but timing violation still exists.

This is my circuit and timing report.

There are two HLS IP in my circuit. My developing IP is bottom one. 

I added my HLS IP based on the circuit published on this github. (https://github.com/fixstars/ultra96_design/tree/master/script)

The original circuit is the circuit for acquiring the camera image of Pcam 5C with Ultra 96 board. The upper HLS IP is used in the original circuit and it is not related my developing HLS IP.

Thanks in advance.

Screenshot from 2019-06-04 03-42-22.pngScreenshot from 2019-06-04 03-36-03.png

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1 Solution

Accepted Solutions
Historian
Historian
428 Views
Registered: ‎01-23-2009

Re: Large Hold time violation in AXI Interconnect

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I agree with @peterk a hold violation of a little more than 100ps is nothing to worry about after synthesis - the hold violation appears to be on the same clock and the tool will fix it during implementation.

However, the report from after implementation shows a 450ps hold time violation, even after the tool's attempt to fix it. This is not the same hold violation - to get a hold violation this big, the failing path has to be between different clocks which have an incorrect relationship. It is (pretty much) impossible for a path with the same startpoint and endpoint clock to result in a hold violation of anywhere near 450ps.

So take a look at the worst failure after place and route and post that result...

Avrum

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5 Replies
Visitor peterk
Visitor
480 Views
Registered: ‎04-08-2018

Re: Large Hold time violation in AXI Interconnect

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You are looking at the synthesized timing results. Don't worry about hold time in sysnthesis results for paths in the same clock domain. Implementation would normally fix them.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc
Contributor
Contributor
475 Views
Registered: ‎11-10-2017

Re: Large Hold time violation in AXI Interconnect

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Thank you for your first reply.

I also tried implementation, but roure_design phase doesn't complete, and after 5-6 hours, it fails with error.

Timing error is very large, and I think implementation cannot solve this violation.

 

Screenshot from 2019-06-04 04-39-00.png
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Scholar watari
Scholar
447 Views
Registered: ‎06-16-2013

Re: Large Hold time violation in AXI Interconnect

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Hi @nittax 

 

Could you share detail timing (path) report log ?

 

I guess clock delay.

So, could you share clock tree, too, if possible ?

 

Best regards,

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Historian
Historian
429 Views
Registered: ‎01-23-2009

Re: Large Hold time violation in AXI Interconnect

Jump to solution

I agree with @peterk a hold violation of a little more than 100ps is nothing to worry about after synthesis - the hold violation appears to be on the same clock and the tool will fix it during implementation.

However, the report from after implementation shows a 450ps hold time violation, even after the tool's attempt to fix it. This is not the same hold violation - to get a hold violation this big, the failing path has to be between different clocks which have an incorrect relationship. It is (pretty much) impossible for a path with the same startpoint and endpoint clock to result in a hold violation of anywhere near 450ps.

So take a look at the worst failure after place and route and post that result...

Avrum

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Contributor
Contributor
375 Views
Registered: ‎11-10-2017

Re: Large Hold time violation in AXI Interconnect

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@peterk @watari @avrumw Thank you for your all reply and deteail explanation.

As a result, now I solved this timing violation after implementation.

First, my HLS IP receives 640pix*480pix*32bit data. When I run implementation the design, route_design process fails after 6hours and hold timing violation exists. I tried to reduce resource utilization of my HLS by using pragma directive on HLS, and re-run the implementation. By doing this, the implementation process could solve the timing violation.

 

Thank you.

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