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Registered: ‎05-24-2013

Logicore IP Divider Generator v3.0 Timing



I am using the Logicore IP Divider Generator v3.0 in my design under ISE 14.7. I am using the Radix-2 algorithm with clocks per division set to 1, since I must get results with each clock. But routing fails most of the time, since the core is too big. I have seen that increasing the clocks per division to 8 and hence reducing the size of the core greatly helps with the routing and timing, but of course the functionality is gone. 


So my question is, would encapsulating the core in pblocks help with the timing issues or does anyone have a better idea?

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Teacher muzaffer
Registered: ‎03-31-2012

Re: Logicore IP Divider Generator v3.0 Timing

@conanind the question is do you need 1 divide output per clock or do you need the divide output next clock after the input is available. If it's former, than you can implement a pipelined divider which would give you a new output every cycle but input valid to first output valid will take multiple cycles. If it's latter, ie you really need a very low latency output, I'd suggest you go back to your requirements and see why you need such a tight requirement, whether you can relax it or whether you can precompute the 1/x of the divider so that the computation you need is a multiplier. 

Dividers are generally difficult, rarely required and sequential, all of which make it difficult to optimize them and people usually find a work-around.

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