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Observer kubilaysavci
Observer
11,248 Views
Registered: ‎12-20-2012

ML605 Virtex-6 MMCM Clock Jitter, ADC and Phase Difference Calculation

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I have a ML605 virtex-6 fpga board and I am trying to find the phase difference of incoming 100MHZ RF signal by sampling and storing it and then calculating the phase. The phase differences I am trying to calculate corresponds to 2-40ps in time domain.

the ADC is FMC150 which is connected to Low Pin Count Connector of the ML605 and uses 250 mhz clock which comes from fpga. This clock is generated via MMCM internally and delivered to the ADC externally from the USER CLK port of FPGA.

The state machine in sync with ADC which runs in the fpga triggers the RF generator and ADC with 10us interval and two consecutive sampling/storing operation is done. This trigger has to be precise in order to prevent sampling mismatch.

 

Question1; Can I reach a precise 10us interval with a state machine counter which uses MMCM 250mhz clk?

Question2; I run into some posts saying that the MMCM output has clk jitter around 90-200ps. In this case, the phase difference I calculate can be due to the MMCM clock jitter itself, right?  Is there any workaround for this problem or  is this project not realizable in the realm of FPGAs? 

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Scholar austin
Scholar
17,830 Views
Registered: ‎02-27-2008

Re: ML605 Virtex-6 MMCM Clock Jitter, ADC and Phase Difference Calculation

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k,

 

1.  Yes.  a synchronous counter running from 250 MHz will precisely count off 10us, over and over again, synchronous to the 250 MHz rising clock edge.  The timing report will tell you the delay from the clock edge to the terminal count.

 

2.  Jitter in the FPGA, from all causes, can be from a few 10's of ps p-p, to as much as a few hundreds of ps peak to pea.

 

So, to find absolute phase is perhaps impossible.  But, to find average phase, is very easy:  average many samples.  As jitter is noise, that will cancel, and leave you with the actual average offset.

 

Using something other than a FPGA will have all the same problems.  Only if you designed your own ASIC might you be able to better this.  Of course, you will also need 50 to 100 million dollars to make your own ASIC...

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar austin
Scholar
17,831 Views
Registered: ‎02-27-2008

Re: ML605 Virtex-6 MMCM Clock Jitter, ADC and Phase Difference Calculation

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k,

 

1.  Yes.  a synchronous counter running from 250 MHz will precisely count off 10us, over and over again, synchronous to the 250 MHz rising clock edge.  The timing report will tell you the delay from the clock edge to the terminal count.

 

2.  Jitter in the FPGA, from all causes, can be from a few 10's of ps p-p, to as much as a few hundreds of ps peak to pea.

 

So, to find absolute phase is perhaps impossible.  But, to find average phase, is very easy:  average many samples.  As jitter is noise, that will cancel, and leave you with the actual average offset.

 

Using something other than a FPGA will have all the same problems.  Only if you designed your own ASIC might you be able to better this.  Of course, you will also need 50 to 100 million dollars to make your own ASIC...

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Observer kubilaysavci
Observer
11,207 Views
Registered: ‎12-20-2012

Re: ML605 Virtex-6 MMCM Clock Jitter, ADC and Phase Difference Calculation

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Is there anybody who tried to average the phase of a signal over many samples in the FPGA? I wonder how many samples should be collected to eliminate the phase noise due to the jitter? p-p jitter is around 100ps

Iam building an FPGA based radar and just trying to estimate how many pulse returns I should store to do the averaging. It is very crucial since it blows up the number of block memories used for storing pulse return signals and thus the overall processing speed decreases due the routing of all signals over these block mems.

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