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Contributor
Contributor
3,757 Views
Registered: ‎02-18-2015

MMCM in Kintex 7 - Clock Capable pin - XDC

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Hi,

I want to generate 2 clocks of 100Mhz and 10Mhz respectively from a primary 100MHz clock that comes as input in a Clock Capable pin. For that, I declared as component and instantiated inside my project an MMCM from the IP Catalog.
The ouput clocks of the MMCM are:
clk_out1 = 100 MHz

clk_out2 = 10 MHz

Both have phase 0 degrees, because I want them to be phase aligned with the input clock.
At the "Optional Inputs" option, I added only a Reset port. No Lock port, no Power Down port.

When I used the clock directly from the CC pin, I had first to instatiate inside my design an IBUFG and a BUFG in order to be able to use the clock. That worked really well.
Now, the clock goes from the CC pin to the input of the MMCM and from there the 2 generated clocks are routed to my design. As I saw in .vhd files that were generated with the MMCM, it already has IBUF and BUFG instantiated inside its files, so I didn't use the ones I had already instantiated.

As for my .XDC file, it is the following:

#create_clock -⁠period 10.000 -⁠name clk_con_int [get_ports clk_con_int]

#################
# CLOCK /⁠ RESET #
#################

#set_false_path -⁠through [get_nets osc_en]
set_property PACKAGE_PIN J8 [get_ports osc_en]
set_property IOSTANDARD LVCMOS25 [get_ports osc_en]
set_property DRIVE 4 [get_ports osc_en]
set_property SLEW SLOW [get_ports osc_en]


########
# GPIO #
########
#NET "k_header<0>"    LOC="D19"  | IOSTANDARD=LVCMOS25 ; # IO_L15P_T2_DQS_15
set_property PACKAGE_PIN D19 [get_ports lbus_drdy]
set_property IOSTANDARD LVCMOS25 [get_ports lbus_drdy]
set_property DRIVE 4 [get_ports lbus_drdy]
set_property SLEW SLOW [get_ports lbus_drdy]
#NET "k_header<1>"    LOC="N17"  | IOSTANDARD=LVCMOS25 ; # IO_L20N_T3_13
#NET "k_header<2>"    LOC="N16"  | IOSTANDARD=LVCMOS25 ; # IO_0_13
#NET "k_header<3>"    LOC="P24"  | IOSTANDARD=LVCMOS25 ; # IO_L4P_T0_13
#NET "k_header<4>"    LOC="E23"  | IOSTANDARD=LVCMOS25 ; # IO_L12N_T1_MRCC_14
#NET "k_header<5>"    LOC="F22"  | IOSTANDARD=LVCMOS25 ; # IO_L12P_T1_MRCC_14
#NET "k_header<6>"    LOC="F23"  | IOSTANDARD=LVCMOS25 ; # IO_L13N_T2_MRCC_14
#NET "k_header<7>"    LOC="G22"  | IOSTANDARD=LVCMOS25 ; # IO_L13P_T2_MRCC_14
#NET "k_header<8>"    LOC="F24"  | IOSTANDARD=LVCMOS25 ; # IO_L14N_T2_SRCC_14
#NET "k_header<9>"    LOC="G24"  | IOSTANDARD=LVCMOS25 ; # IO_L14P_T2_SRCC_14


#-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠ Local bus
#############################################
# Spartan-⁠6 HPIC (LVCMOS15, SSTL15 or HTSL) #
#############################################
set_property PACKAGE_PIN AB11 [get_ports clk_con_int]
set_property IOSTANDARD LVCMOS15 [get_ports clk_con_int]

#NET "reset"   LOC="AC11" |IOSTANDARD=LVCMOS15;

set_property PACKAGE_PIN AA13 [get_ports lbus_rst]
set_property IOSTANDARD LVCMOS15 [get_ports lbus_rst]

set_property PACKAGE_PIN AE10 [get_ports lbus_dvld]
set_property IOSTANDARD LVCMOS15 [get_ports lbus_dvld]
set_property DRIVE 4 [get_ports lbus_dvld]
set_property SLEW SLOW [get_ports lbus_dvld]


set_property PACKAGE_PIN V4 [get_ports {lbus_do[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[0]}]
set_property DRIVE 4 [get_ports {lbus_do[0]}]
set_property SLEW SLOW [get_ports {lbus_do[0]}]

set_property PACKAGE_PIN V2 [get_ports {lbus_do[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[1]}]
set_property DRIVE 4 [get_ports {lbus_do[1]}]
set_property SLEW SLOW [get_ports {lbus_do[1]}]

set_property PACKAGE_PIN W1 [get_ports {lbus_do[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[2]}]
set_property DRIVE 4 [get_ports {lbus_do[2]}]
set_property SLEW SLOW [get_ports {lbus_do[2]}]


set_property PACKAGE_PIN AB1 [get_ports {lbus_do[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[3]}]
set_property DRIVE 4 [get_ports {lbus_do[3]}]
set_property SLEW SLOW [get_ports {lbus_do[3]}]

set_property PACKAGE_PIN Y3 [get_ports {lbus_do[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[4]}]
set_property DRIVE 4 [get_ports {lbus_do[4]}]
set_property SLEW SLOW [get_ports {lbus_do[4]}]

set_property PACKAGE_PIN U7 [get_ports {lbus_do[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[5]}]
set_property DRIVE 4 [get_ports {lbus_do[5]}]
set_property SLEW SLOW [get_ports {lbus_do[5]}]

set_property PACKAGE_PIN V3 [get_ports {lbus_do[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[6]}]
set_property DRIVE 4 [get_ports {lbus_do[6]}]
set_property SLEW SLOW [get_ports {lbus_do[6]}]

set_property PACKAGE_PIN AF10 [get_ports {lbus_do[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[7]}]
set_property DRIVE 4 [get_ports {lbus_do[7]}]
set_property SLEW SLOW [get_ports {lbus_do[7]}]

set_property PACKAGE_PIN AC13 [get_ports {lbus_do[8]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[8]}]
set_property DRIVE 4 [get_ports {lbus_do[8]}]
set_property SLEW SLOW [get_ports {lbus_do[8]}]

set_property PACKAGE_PIN AE12 [get_ports {lbus_do[9]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[9]}]
set_property DRIVE 4 [get_ports {lbus_do[9]}]
set_property SLEW SLOW [get_ports {lbus_do[9]}]

set_property PACKAGE_PIN U6 [get_ports {lbus_do[10]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[10]}]
set_property DRIVE 4 [get_ports {lbus_do[10]}]
set_property SLEW SLOW [get_ports {lbus_do[10]}]

set_property PACKAGE_PIN AE13 [get_ports {lbus_do[11]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[11]}]
set_property DRIVE 4 [get_ports {lbus_do[11]}]
set_property SLEW SLOW [get_ports {lbus_do[11]}]

set_property PACKAGE_PIN AA10 [get_ports {lbus_do[12]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[12]}]
set_property DRIVE 4 [get_ports {lbus_do[12]}]
set_property SLEW SLOW [get_ports {lbus_do[12]}]

set_property PACKAGE_PIN AB12 [get_ports {lbus_do[13]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[13]}]
set_property DRIVE 4 [get_ports {lbus_do[13]}]
set_property SLEW SLOW [get_ports {lbus_do[13]}]

set_property PACKAGE_PIN AA4 [get_ports {lbus_do[14]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[14]}]
set_property DRIVE 4 [get_ports {lbus_do[14]}]
set_property SLEW SLOW [get_ports {lbus_do[14]}]

set_property PACKAGE_PIN AE8 [get_ports {lbus_do[15]}]
set_property IOSTANDARD LVCMOS15 [get_ports {lbus_do[15]}]
set_property DRIVE 4 [get_ports {lbus_do[15]}]
set_property SLEW SLOW [get_ports {lbus_do[15]}]


########################################
# Spartan-⁠6 HRIC (LVCMOS25 or LVDS_25) #
########################################
set_property PACKAGE_PIN T22 [get_ports {lbus_di[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[0]}]


set_property PACKAGE_PIN M24 [get_ports {lbus_di[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[1]}]


set_property PACKAGE_PIN K25 [get_ports {lbus_di[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[2]}]


set_property PACKAGE_PIN R26 [get_ports {lbus_di[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[3]}]


set_property PACKAGE_PIN M25 [get_ports {lbus_di[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[4]}]


set_property PACKAGE_PIN U17 [get_ports {lbus_di[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[5]}]


set_property PACKAGE_PIN N26 [get_ports {lbus_di[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[6]}]


set_property PACKAGE_PIN R16 [get_ports {lbus_di[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[7]}]


set_property PACKAGE_PIN T20 [get_ports {lbus_di[8]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[8]}]


set_property PACKAGE_PIN R22 [get_ports {lbus_di[9]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[9]}]


set_property PACKAGE_PIN M21 [get_ports {lbus_di[10]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[10]}]


set_property PACKAGE_PIN T24 [get_ports {lbus_di[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[11]}]


set_property PACKAGE_PIN P23 [get_ports {lbus_di[12]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[12]}]


set_property PACKAGE_PIN N21 [get_ports {lbus_di[13]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[13]}]


set_property PACKAGE_PIN R21 [get_ports {lbus_di[14]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[14]}]


set_property PACKAGE_PIN N18 [get_ports {lbus_di[15]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_di[15]}]



set_property PACKAGE_PIN T23 [get_ports {lbus_a[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[0]}]

set_property PACKAGE_PIN L24 [get_ports {lbus_a[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[1]}]


set_property PACKAGE_PIN K26 [get_ports {lbus_a[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[2]}]


set_property PACKAGE_PIN P26 [get_ports {lbus_a[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[3]}]


set_property PACKAGE_PIN L25 [get_ports {lbus_a[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[4]}]


set_property PACKAGE_PIN T17 [get_ports {lbus_a[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[5]}]


set_property PACKAGE_PIN M26 [get_ports {lbus_a[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[6]}]


set_property PACKAGE_PIN R17 [get_ports {lbus_a[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[7]}]


set_property PACKAGE_PIN R20 [get_ports {lbus_a[8]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[8]}]


set_property PACKAGE_PIN R23 [get_ports {lbus_a[9]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[9]}]


set_property PACKAGE_PIN M22 [get_ports {lbus_a[10]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[10]}]


set_property PACKAGE_PIN T25 [get_ports {lbus_a[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[11]}]


set_property PACKAGE_PIN N23 [get_ports {lbus_a[12]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[12]}]


set_property PACKAGE_PIN N22 [get_ports {lbus_a[13]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[13]}]


set_property PACKAGE_PIN P21 [get_ports {lbus_a[14]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[14]}]


set_property PACKAGE_PIN M19 [get_ports {lbus_a[15]}]
set_property IOSTANDARD LVCMOS25 [get_ports {lbus_a[15]}]


set_property PACKAGE_PIN P18 [get_ports lbus_rd]
set_property IOSTANDARD LVCMOS25 [get_ports lbus_rd]

set_property PACKAGE_PIN R18 [get_ports lbus_wr]
set_property IOSTANDARD LVCMOS25 [get_ports lbus_wr]

set_property PACKAGE_PIN U19 [get_ports lbus_rd_ACK]
set_property IOSTANDARD LVCMOS25 [get_ports lbus_rd_ACK]

As you can see, I have commented out the constraint

#create_clock -⁠period 10.000 -⁠name clk_con_int [get_ports clk_con_int]

and I did that because as I saw, Vivado takes into account also the XDC file that is automatically generated for the MMCM (or so I think):

# file: clk_wiz_0.xdc
#
# (c) Copyright 2008 -⁠ 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-⁠
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-⁠
# safe, or for use in any application requiring fail-⁠safe
# performance, such as life-⁠support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
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# (individually and collectively, "Critical
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#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#

# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system. If required
# commented constraints can be used in the top level xdc
#-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠-⁠
# Connect to input port when clock capable pin is selected for input
create_clock -⁠period 10.0 [get_ports clk_con_int]
set_input_jitter [get_clocks -⁠of_objects [get_ports clk_con_int]] 0.1

Although the bitstream is generated without giving me any errors or critical warnings (or even simple warnings regarding timing/clocks), when I try to test my design (the Kintex 7 is inteconnected with a Spartan 6 that acts as the 'Control' FPGA) I don't get anythiing in response. I have downloaded also an ILA core inside the Kintex 7, but still I don't get anything in return (even the triggering signal that comes from the Spartan 6, is not triggered).
I am assuming that my problem has to do the output clocks of my MMCM. To put it plain and simple I think that no clocks are generated.

Can anyone confirm that my .XDC is written right?
I am using Vivado 2014.2 and the Kintex 7 is a xc7k160tfbg676.

Thank you in advance for your responses.
Nassos

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Accepted Solutions
Highlighted
Contributor
Contributor
6,186 Views
Registered: ‎02-18-2015

Re: MMCM in Kintex 7 - Clock Capable pin - XDC

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@ashishd

Apparently it had something to do with the problem I faced here:
https://forums.xilinx.com/t5/Synthesis/Nets-missing-in-Netlist-Vivado-2014-2/m-p/751142/highlight/true#M20822
Once the above problem was solved, my component alongside with the MMCM started functioning correctly.

Just for the record, the format of my .XDC file works correctly (Vivado takes into account the .XDC file of the MMCM). Also no IBUFG/BUFG inserted manually by me, as MMCM by itself undertakes that task.

P.S.
Excuse me for my late reply, I have been really busy in parallel, with other aspects of my project. Thank you again for the great work all of you guys (Moderators/Employees/Teachers) do in this forum.

Kind regards,
Nassos

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3 Replies
Xilinx Employee
Xilinx Employee
3,740 Views
Registered: ‎02-14-2014

Re: MMCM in Kintex 7 - Clock Capable pin - XDC

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Hello @anm,

 

Have you performed post-implementation functional simulation for your design?

Do you observe expected behavior there?

Regards,
Ashish
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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Highlighted
Contributor
Contributor
6,187 Views
Registered: ‎02-18-2015

Re: MMCM in Kintex 7 - Clock Capable pin - XDC

Jump to solution

@ashishd

Apparently it had something to do with the problem I faced here:
https://forums.xilinx.com/t5/Synthesis/Nets-missing-in-Netlist-Vivado-2014-2/m-p/751142/highlight/true#M20822
Once the above problem was solved, my component alongside with the MMCM started functioning correctly.

Just for the record, the format of my .XDC file works correctly (Vivado takes into account the .XDC file of the MMCM). Also no IBUFG/BUFG inserted manually by me, as MMCM by itself undertakes that task.

P.S.
Excuse me for my late reply, I have been really busy in parallel, with other aspects of my project. Thank you again for the great work all of you guys (Moderators/Employees/Teachers) do in this forum.

Kind regards,
Nassos

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Xilinx Employee
Xilinx Employee
3,552 Views
Registered: ‎02-14-2014

Re: MMCM in Kintex 7 - Clock Capable pin - XDC

Jump to solution

Hello @anm,

 

Good to know that reference of previous thread helped in this case.

Close the thread by marking helpful post as solution in the interest of other users.

Regards,
Ashish
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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