11-24-2020 07:34 PM
How can I estimate the clock frequency of my design manually (using the parameters for a target device)?
Can I please see an example.
11-27-2020 11:15 AM - edited 11-27-2020 11:16 AM
1. Select your target device.
2. Come up with a dummy small design representative of your actual design (clock speed, levels of logic between registers, timing scenarios, clock domain crossings, timing exceptions, etc. ).
3. Do a build
4. Look at time reports.
11-27-2020 11:41 AM
What do you mean by manually ?
Anyway with the interconnects having a bigger and bigger contributions in recent FPGA technologies, and with the tendency to have routing congestion when your FPGA is pretty full (although the phenomenom can also appear locally), if you plan to run at a high frequency wrt to the FPGA family you use, you won't have any good estimate without having a quick and dirty place and route of your design.
11-29-2020 09:55 PM
This AR might be helpful for you: