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Observer
Observer
358 Views
Registered: ‎11-24-2020

Manual Estimate of Clock Frequency

How can I estimate the clock frequency of my design manually (using the parameters for a target device)?
Can I please see an example.

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3 Replies
Scholar
Scholar
290 Views
Registered: ‎06-20-2017

1.  Select your target device.

2.  Come up with a dummy small design representative of your actual design (clock speed, levels of logic between registers, timing scenarios, clock domain crossings, timing exceptions, etc. ).

3.  Do a build

4.  Look at time reports.

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Participant
Participant
280 Views
Registered: ‎11-21-2020

What do you mean by manually ?

Anyway with the interconnects having a bigger and bigger contributions in recent FPGA technologies, and with the tendency to have routing congestion when your FPGA  is pretty full (although the phenomenom can also appear locally), if you plan to run at a high frequency wrt to the FPGA family you use, you won't have  any good estimate without having a quick and dirty place and route of your design.

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Xilinx Employee
Xilinx Employee
199 Views
Registered: ‎05-14-2008

This AR might be helpful for you:

https://www.xilinx.com/support/answers/57304.html

-vivian

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