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hasaney
Adventurer
Adventurer
9,787 Views
Registered: ‎03-06-2011

Max Frequency of BRAM not found in Timing Report?

Hello,

 

Nowadays, I am working on speed of different BRAM configurations (Xilinx Vİrtex5, ISE 14.4).

 

FIRST CONFIGURATION;

 

capture1.PNG

 

IN  the basic design consists of a BRAM connected directly to output ports (above), I could not get the timing results.  OK it is not problem. Xilinx Tool computes the timing between two FFs. So I registered to output to measure the timing and added a FF.

 

SECOND CONFIGURATION

 

Capture2.PNG

 

 

 

 

 

 

 

 

 

 

 

In this configuration Post RAR Static Timing report says that design can run @ 3.78 ns (260 Mhz).

 

This is the basic configuration of block RAM and I have already know that BRAM can work at higher speeds (more than 500 Mhz)

My prediction is that the problem may be caused because of P&R such that FF is placed far away from BRAM. 

 

If you give me some explanations, I will be very pleased.

 

Thanks.

 

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11 Replies
austin
Scholar
Scholar
9,779 Views
Registered: ‎02-27-2008

H,


If you look at the verbose timing report, you will see the delays in each path broken down into the components.

 

Or, you could examine the path in FPGA_Editor, and identify the longest delay in the path.

 

Yes:  the further away to DFF is, the longer the delay in getting to it.  Proper constraints will have the tools place the DFF properly.

 

To find the fastest speed a design may operate at, you need to "sneak up" on it:  the tools are designed to do the job and meet timing, and no more than that.  So, you sdhould keep decreasing the period constraint until the design fails, and then keep decreasing it a bit more.  An even faster frequency will often work, whikle a slower one failed just due to random placement issues.  When you get slose to the performance limit, the design alternately passes or fails with the most trivial changes (a good sign you are too close to the limit, along with small slack values).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
hasaney
Adventurer
Adventurer
9,767 Views
Registered: ‎03-06-2011

Thanks Mr. Austin a lot.

 

I am wondering one thing more. In fack, I have nothing to do with input and output pads, that is, the pads goes to bram and goes to pads from output of FF. Only BRAM to FF speed is important for me. It is a part of a system. For this reason, I changed the Synthesis Options as " no add I/O buffers" and in map properties trim unconnected signals are unchecked.  However in this case, verbose report did not give any information about timing only systhesis says;

 

Minimum period: No path found         (this information shold be provided because there is a path between BRAM and FF)
Minimum input arrival time before clock: 0.000ns    ( why provided? Because input signals are trimmed)
Maximum output required time after clock: 0.396ns   ( why provided? Because output signals are trimmed)
Maximum combinational path delay: No path found (OK)

 

and How can obtain the exact working speed without regarding i/o pads.

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blasm
Xilinx Employee
Xilinx Employee
9,744 Views
Registered: ‎08-17-2011

Hi,

 

If you are concern about the speed/delay from BRAM to FFs without regarding the IO pads FFs. why not to add the IO buffers with IO registers and then place aditional FFs for input/output of the RAMB18 in your test design?
Using PlanAhead you could place the components as close as you want or any other location that suits you.
Then apply the PERIOD constraint or if need it a FROM ... TO between the BRAM and the FFs.

 

Also bare on mind BRAM18 configuration and the read-write clocks applied.

 

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hasaney
Adventurer
Adventurer
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Registered: ‎03-06-2011

Thanks Blesm, I am very pleased for your answer. 

 

However I counn't understand some points.

 

Are you mention about synthesize -> xilinx specific options -> -iobuf (add i/o buffers) and -iob (Pack I/O registers into IOBS) b?

 

In this case circuit becomes;

 

IO (Pİn) -> IO Register -> Additional Input FFs -> BRAM -> Additional Output FFs -> IO(Pİn)

 

In this case tool may say that longest delay is between IO Register  and Additional Input FFs.

 

In fact, I am only dealing with internal runnign frequency of a synchronous design not concerned about IOs.

--
Thanks
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blasm
Xilinx Employee
Xilinx Employee
9,715 Views
Registered: ‎08-17-2011

I understand you are not concern about the IO registers but you would like to know the delay between the RAMB and the FFs so ignoring the Timing analysis for the IO Registers you only need to look at the path-delay between RAMB and FFs.

The recommended circuit would be:
IO (Pİn) -> IO Register -> Additional Input FFs -> BRAM -> Additional Output FFs -> IO Register -> IO(Pİn).

As Austin said: " the tools are designed to do the job and meet timing, and no more than that".
So it is not going to tell you what is the lowest freq you can run from BRAM to FFs, this depends on some constraints.
If you want to find out what is the highest freq the tool can achieve without passing any placement constraint then follow Austin idea.
If you want to find the highest freq between RAMB and the FFs, then constraint them as close as possible and make sure there is a constraint where the output path is reported.
Basic rule:
"the further away to DFF is, the longer the delay in getting to it".
hasaney
Adventurer
Adventurer
9,701 Views
Registered: ‎03-06-2011

Thanks blasm,

 

There is one thing that i forgot. If i don't trim the IO  connections/ports and add IO buffers then ISE says "there is no enough resource for IOs". My IO connections are more than Virtex 5 allowed.

 

What can i do in a such situration?

 

Thanks.

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hasaney
Adventurer
Adventurer
9,687 Views
Registered: ‎03-06-2011

if I/O connections of the internal circuit which I try to measure speed is higher than the FPGA I/O resources, tool  gives the error "no enugh resorce". In a such situation, what can i do? 

 

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bassman59
Historian
Historian
9,683 Views
Registered: ‎02-25-2008


@hasaney wrote:

if I/O connections of the internal circuit which I try to measure speed is higher than the FPGA I/O resources, tool  gives the error "no enugh resorce". In a such situation, what can i do? 

 


You should probably try to work on a real design instead of doing this sort of theoretical test.

----------------------------Yes, I do this for a living.
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hasaney
Adventurer
Adventurer
9,681 Views
Registered: ‎03-06-2011

The designed circuit is an internal circuit that can be connected any other circuit. This is a real world case. In this step I am only dealing with internal one and not working on whole design.

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hgleamon1
Teacher
Teacher
5,638 Views
Registered: ‎11-14-2011

You seem to be going about this if not backwards then certainly from a strange angle.

 

All this talk about "maximum frequency" is, in my opinion, irrelevant. The tools, as pointed by Austin ages ago, deal with constraints. You want your design to run at a given frequency? Set that as the input clock constraint and THEN run the tools. Once your design passes timing, great. If it fails timing then you can look at the failing paths and deal with them accordingly.

 

You will get no useful data, I believe, fiddling around with theory and "internal designs" in this manner.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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hasaney
Adventurer
Adventurer
5,626 Views
Registered: ‎03-06-2011

Thanks again for the replies.

 

I agree with you about what the tool does. Ok tool tries to comply with constraints. However decreasing constraints and findind a break point, i can find the maximum speed as austing says.

 

In addition to this, I think tool can give me some results about interior designs (without IO). 

 

In this document, http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf it was stated that BRAM can work at 550 Mhz with -3 speed grade. 

 

and when i remove the IO and implement this code it gives the this speed (550 Mhz).

-- BRAM _DSP is simple dual mode BRAM.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

library UNISIM;
use UNISIM.VComponents.all;

entity MultiPort is
port(
    CLK_BRAM    : IN    STD_LOGIC;
    EN            : IN    STD_LOGIC;
    ADDR_R0_REG    : IN    STD_LOGIC_VECTOR(8 DOWNTO 0);
    ADDR_W0_REG    : IN    STD_LOGIC_VECTOR(8 DOWNTO 0);
    DI_W0_REG        : IN    STD_LOGIC_VECTOR(63 DOWNTO 0);
    WE_W0_REG        : IN    STD_LOGIC;
    DO_R0_REG        : OUT    STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end MultiPort;


architecture Behavioral of MultiPort is

    Component BRAM_SDP
    PORT(
        CLK    : IN std_logic;
        EN        : IN std_logic;
        RADDR    : IN std_logic_vector(8 downto 0);
        WADDR    : IN std_logic_vector(8 downto 0);
        DI        : IN std_logic_vector(63 downto 0);
        WE        : IN std_logic;
        DO        : OUT std_logic_vector(63 downto 0)
    );
    END COMPONENT;
   
    signal ADDR_R0    :STD_LOGIC_VECTOR(8 DOWNTO 0);
    signal ADDR_W0    :     STD_LOGIC_VECTOR(8 DOWNTO 0);
     signal DI_W0        :    STD_LOGIC_VECTOR(63 DOWNTO 0);
    signal WE_W0    :    STD_LOGIC;
    signal DO_R0        : STD_LOGIC_VECTOR(63 DOWNTO 0);

begin
    process(CLK_BRAM)
    begin
        if(rising_edge(CLK_BRAM)) then
            ADDR_R0 <= ADDR_R0_REG;
            ADDR_W0 <= ADDR_W0_REG;
            DI_W0 <= DI_W0_REG;
            WE_W0 <= WE_W0_REG;
            DO_R0_REG <= DO_R0;
        end if;
    end process;
   
    Inst_BRAM_B0R0: BRAM_SDP
    PORT MAP(
        CLK => CLK_BRAM,
        EN => EN,
        RADDR => ADDR_R0,
        WADDR => ADDR_W0,
        DI => DI_W0,
        WE => WE_W0,
        DO => DO_R0
    );

   
end Behavioral;

 

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