Max pluse wdith skew timing violations in DDR3 mig core
My design recently started failing timing for clock skew between PLL_CLK and RIU_CLK port in ddr3 mig core .
My device is xcku040-ffva1156 and my vivado version is 2017.4. This is the timing report. This is the relevant path RTL. So I have a few questions about this issue: 1.What is the definition of Pluse wdith? 2.How to calculate the "required" and "actual" of Pluse wdith. 3.What should I do about this problem?
English is not my native language and I apologize for my expression.