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Observer
Observer
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Registered: ‎07-18-2018

Max pluse wdith skew timing violations in DDR3 mig core

My design recently started failing timing for clock skew between PLL_CLK and RIU_CLK port in ddr3 mig core .

My device is xcku040-ffva1156 and my vivado version is 2017.4.
This is the timing report.
q1.png
This is the relevant path RTL.
q2.png
So I have a few questions about this issue:
1.What is the definition of Pluse wdith?
2.How to calculate the "required" and "actual" of Pluse wdith.
3.What should I do about this problem?

Thanks !

English is not my native language and I apologize for my expression.

-D

q1.png
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Observer
Observer
401 Views
Registered: ‎07-18-2018

I tried the solution provided by AR# 68169, but it didn't work. what should I do?
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