Maximum Clock on Virtex UltraScale+

[thilinap]

Hi,

May I please know the maximum achievable clock on a Virtex Ultrascale+ FPGA, after the implementation phase is complete.

[drjohnsmith]

Thats a null question, but we get asked it often.

You need to up your understanding of FPGAs.

A quick introduction.

FPGAs are user defined logic.
the chisp themselfs have various units, multipliers, rams, registers, logic tables (LUT ) , Io pins, internal delays.

which look in the data sheet for the part you are looking at , you will see a speed.

But it depends how you wire up the units,
think of it like lego, made of various blocks.
you could ask the question, how big can I make a LEGO model ?
its impossible to say as its limited by what you design.

same with FPGas.

If you just string registers which are fast together they run at one speed,
if you string the registers, with lots of slow gates between, they will run slower.

In conclusion,
its part of being a FPGA engineer you will only learn with experience, practicing and making mistakes.

[thilinap]

I suppose my question was misinterpreted. I understand all that you say.
But isn't all this limited by the oscillator on the chip? 
What I really want to know is on a best case what is roughly the maximum frequency achievable in the device family

[bruce_karaffa]

There is no oscillator on the chip.  You can look in the data sheet to find the  maximum frequency supported by the clock buffers but as a rule, no practical design will run that fast.  As @drjohnsmith mentioned, the speed that a design may run is dictated by that design.

[thilinap]

Just found this, in the post below.

Fmax for a -3 Virtex UltraScale + device is 891 Mhz. See DS 923 page 30:

https://forums.xilinx.com/t5/Versal-and-UltraScale/Could-Virtex-UltraScale-FPGA-run-at-1G-HZ/td-p/820783

Guess it's legit?

[drjohnsmith]

The oscilator on the chip is a PLL, in a lot of the chips this can runs at over a GHz,
but that tells you nothing about how fast your design can work.

This is not a processor, FPGAs are massively parallel,
think of a human brain,
its clock speed is meant to be in the region of 1 KHz
but its massively parallel.

[drjohnsmith]

Re
Fmax for a -3 Virtex UltraScale + device is 891 Mhz

Yep thats totaly legitimate,

but its marketing speak.
I think its for the output of a register connected direct back to its input , i assume your design is doing more than that ,

[thilinap]

True. However, won't options like Phy opt bring the clock to a significantly high value?

[drjohnsmith]

explain please your understanding of "Phy opt"

[thilinap]

Physical Optimization in Vivado. This works on place and route and usually significantly increases the clock. It lets you select your optimisation goals, costly interms of tool runtime.

[drjohnsmith]

OK, yep there are options to make the tools work harder to fit your design

but if you design a 128 input logic gate, with a single register , there is no way that is going to run as fast as say a two input or gate and a single register.

Now you could re code, to make the 128 input logic gate , take say 8 register delays, and that would be faster,
given the registers, the tools can do some tricks,
but the tools can not change your logic function

sorry, this is where experience comes in

My best advise is, do some dummy designs of what you expect to be using, and try them out in the chips, see what timing you can get down to,

[thilinap]

To clarify, I was just trying to see what the maximum practical value is. I have a relatively large design, that generates the bit stream successfully at a very fast clock frequency after phys opt. hence, the original question. 

I never disagreed with your argument, but my question was different. Thank you for your time. 

[drjohnsmith]

in that case,
500 relatively easily,

750 probably