11-24-2020 12:58 AM
May I please know the maximum achievable clock on a Virtex Ultrascale+ FPGA, after the implementation phase is complete.
11-24-2020 02:35 AM
11-24-2020 03:44 AM
I suppose my question was misinterpreted. I understand all that you say.
But isn't all this limited by the oscillator on the chip?
What I really want to know is on a best case what is roughly the maximum frequency achievable in the device family
11-24-2020 04:16 AM
There is no oscillator on the chip. You can look in the data sheet to find the maximum frequency supported by the clock buffers but as a rule, no practical design will run that fast. As @drjohnsmith mentioned, the speed that a design may run is dictated by that design.
11-24-2020 04:30 AM
Just found this, in the post below.
Fmax for a -3 Virtex UltraScale + device is 891 Mhz. See DS 923 page 30:
Guess it's legit?
11-24-2020 06:04 AM
11-24-2020 06:05 AM
11-24-2020 09:33 AM - edited 11-24-2020 09:35 AM
Physical Optimization in Vivado. This works on place and route and usually significantly increases the clock. It lets you select your optimisation goals, costly interms of tool runtime.
11-24-2020 10:03 AM
11-24-2020 10:37 AM - edited 11-24-2020 10:38 AM
To clarify, I was just trying to see what the maximum practical value is. I have a relatively large design, that generates the bit stream successfully at a very fast clock frequency after phys opt. hence, the original question.
I never disagreed with your argument, but my question was different. Thank you for your time.