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Explorer
Explorer
290 Views
Registered: ‎07-10-2013

Meeting Timing In Spite Of An Asynchronous Clock

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Consider a two-input LUT, each input being produced by the output of a separate clocked flipflop, with the LUT output feeding the D input of a third clocked flipflop.  With all three flipflops clocked by the same clock, and with a clock period timing constraint specified, Vivado would work to ensure that the signal in to the output flipflop mets timing.

Suppose instead that one of the LUT-input flipflops is clocked by a second clock that is completely unrelated (asynchronous) to the first clock.  Will Vivado decide since the timing of that path is unknown that the timing of the LUT output might not be able to be determined, and will therefore make no effort to optimize the timing of the other path through the LUT and in to the output flipflop?

Or, will Vivado essentially ignore the asynchronous path in to the LUT, and proceed as before to optimize the timing of the other path?

 

 

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Xilinx Employee
Xilinx Employee
264 Views
Registered: ‎05-14-2008

Re: Meeting Timing In Spite Of An Asynchronous Clock

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Timing paths start from and end at sequential elements like flip-flops, RAMs, DSPs and so on.

So in the circuits you described, you have two timing paths.

FF1 -> LUT -> FF3

FF2 -> LUT -> FF3

To guarantee the FF3 captures the correct data, both paths need to meet timing.

If FF1 and FF3 are clocked by two asynchronous clocks (say you've let the tool know this by set_clock_groups), Vivado will not do any timing analysis or any timing-driven optimization on this path.

However, FF2 and FF3 are clocked by the same clock, Vivado will analyze this path and try to make it meet timing.

Hope this helps.

-vivian

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Moderator
Moderator
272 Views
Registered: ‎11-04-2010

Re: Meeting Timing In Spite Of An Asynchronous Clock

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Hi, @chsdkj ,

For the asynchrnous timing paths bwtween 2 clocks without relationship, Vivado will analyze the timing for the path in default.  The requirement of the path will be calculated depend on the period & phase of 2 asynchronous clocks, but this path is still unsafe, because in fact, the no one knows the default start time of 2 clocks. 

For such asynchronous path, you have to use logic to promise the function correctness, such as handshaking, FIFO... , instead of letting tool analyzing it automatically.

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Xilinx Employee
Xilinx Employee
265 Views
Registered: ‎05-14-2008

Re: Meeting Timing In Spite Of An Asynchronous Clock

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Timing paths start from and end at sequential elements like flip-flops, RAMs, DSPs and so on.

So in the circuits you described, you have two timing paths.

FF1 -> LUT -> FF3

FF2 -> LUT -> FF3

To guarantee the FF3 captures the correct data, both paths need to meet timing.

If FF1 and FF3 are clocked by two asynchronous clocks (say you've let the tool know this by set_clock_groups), Vivado will not do any timing analysis or any timing-driven optimization on this path.

However, FF2 and FF3 are clocked by the same clock, Vivado will analyze this path and try to make it meet timing.

Hope this helps.

-vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Historian
Historian
212 Views
Registered: ‎01-23-2009

Re: Meeting Timing In Spite Of An Asynchronous Clock

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Let's be clear here...

If you have a path that starts at a flip-flop on one clock, goes through combinatorial logic and ends at a flip-flop on an unrelated clock, then this is an illegal clock crossing.

Any time you need to move data from one unrelated clock domain to another, you need a clock domain crossing circuit (CDCC). The design of this CDCC depends entirely on the kind of data being crossed - whether it is a single bit or a bus, whether it is slow changing (no more than once every N clocks) or fast changing, whether it has a known sequence (and a bunch of others).

When you implement a CDCC, the requirements on the paths crossing between domains within the CDCC are determined by the above requirements and the structure of the CDCC. The default timing analysis done by the tool is not correct - the tools assume the two domains are synchronous and time them accordingly. Therefore a timing exception is required - not necessarily to remove the timing check (as the set_clock_groups command does) - it is only one of the possible exceptions that may be the right one for a CDCC.

However, one characteristic that all (or at least almost all) CDCCs have is that the paths between domains must be direcly flip-flop to flip-flop. Since your description above has it going through a LUT, it is almost certainly an illegal clock domain crossing.

So, the question is not "how to get it to meet timing", but instead "how to design a circuit that will work when multiple unrelated clocks are involved".

Avrum