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Observer
Observer
6,126 Views
Registered: ‎11-18-2015

Multicycle paths with Vivado and Synplify

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Hi all,

 

I am using a synthesis flow where I perform synthesis with Synplify Pro, and then perform P&R with Vivado.

 

I would like to relax constraints for some signals by setting a multicycle path. But I was wondering...

 

Should I define the constraint in Synplify only? Vivado only? Both?

 

I believe the correct thing to do would be to mark the registers with a *keep* attribute at synthesis and then constraint the multicycle path only at P&R. What do you think?

 

Thanks for your feedback!

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Xilinx Employee
Xilinx Employee
11,446 Views
Registered: ‎05-07-2015

HI @al_gm

 

Yes.

As the post P&R timing analysis is what that matters.

Once you import the synthesized netlist from synplify into vivado. You can identify the register-registers path which needs  the multicycle path exceptions and apply them in an xdc file,  which will be used for implementation(P&R).

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
11,447 Views
Registered: ‎05-07-2015

HI @al_gm

 

Yes.

As the post P&R timing analysis is what that matters.

Once you import the synthesized netlist from synplify into vivado. You can identify the register-registers path which needs  the multicycle path exceptions and apply them in an xdc file,  which will be used for implementation(P&R).

Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

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