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evg_xilinx
Visitor
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Registered: ‎07-07-2009

Multiple Asynchronous Clock Domains Crossing Problem

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Good day!

 

I have a problem, on which I'm hanging on for a long time. In my project I have four (4) master clocks from four ADC (AD7763) channels, which are connected to Spartan-6 (XC6SLX9-TQG144), and one (1) SYS_CLK, which is derived from PLL_ADV inside FPGA. ADC_CLK = 18,432 Mhz, SYS_CLK = 160 Mhz (derived from 40 Mhz VXCO + PLL_ADV multiplier).

My project has strict requirements on galvanic isolation of ADC modules, so the only variant is to use separate clock source on each ADC channel, as master clock. Unfortunately clocks are a bit different (+/- 1-2 Hz) in each ADC channel, and I think this is the source of all my troubles.

The problem is that when I'm trying to get data from more than two (2) ADC channels, I have omissions of data, which looks like parts of signal are overwriting sometimes and that process is unpredictable and unperiodical strongly. When I use only two (2) ADC channels the picture looks much more good, but not ideal, there are also ommissions sometimes, but more rare.

I have tried to use design technics, which eliminates metastable conditions in triggers (double buffers for signals on cross domain paths), and also write timing constraints in UCF for Asynchronous Clock Domains using DATAPATHONLY keyword, but the problem is still here... so I just have no more variants to verify.

 

If anybody can give advice, what I can try is another solution, please help.

 

In advance thanks,

Evgenyy.

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muzaffer
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29,190 Views
Registered: ‎03-31-2012

So you have 5 clock domains, 4 from ADCs and 1 system clock? Then you need 4 asynchronous FIFOs to bring each ADC data to the system clock domain. Make sure that your system clock (ie the FPGA side clock of each async fifo) to be (at least) slightly faster than any of the ADC clocks and manage data underflows at the system clock side for each ADC.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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muzaffer
Teacher
Teacher
29,191 Views
Registered: ‎03-31-2012

So you have 5 clock domains, 4 from ADCs and 1 system clock? Then you need 4 asynchronous FIFOs to bring each ADC data to the system clock domain. Make sure that your system clock (ie the FPGA side clock of each async fifo) to be (at least) slightly faster than any of the ADC clocks and manage data underflows at the system clock side for each ADC.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

evg_xilinx
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21,815 Views
Registered: ‎07-07-2009

Thank you, muzaffer. This helped a lot!

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