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dharpeer
Adventurer
Adventurer
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Registered: ‎11-24-2020

Multiple clocks on same object

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Hi,

In a Xilinx document, I came across the following,

create_clock -name clk1 -period 10 [get_ports clk_in1]
create_clock -name clk2 -period 5 [get_ports clk_in1] -add

As per the document both clocks are attached to the same port. I am confused as to how this can be done, given it is the same port.

Thanks in advance.

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hongh
Moderator
Moderator
328 Views
Registered: ‎11-04-2010

Hi, @dharpeer ,

Yes, in this way, both clocks will detected and work in the design.

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hongh
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Registered: ‎11-04-2010

You can image a scenario in which the input clock frequency will be switched. Sometimes the design will work for 200Mhz and sometimes the design will work for 100Mhz. Of course, these 2 frequency can not work at the same time.

With your 2 clock constraints, tool can calculate whether 2 clocks of the different frequency can work properly in the design.

Since 2 clocks on the same port cannot work physically at the same time, the paths between these 2 clocks should be ignored.

The below constraint should also be added to avoid unreasonable data path analysis:

Ex:  set_clock_groups -physically_exclusive -group [get_clocks clk1] -group [get_clocks clk2] 

 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

can you share a link to the doc and reference please

 

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dharpeer
Adventurer
Adventurer
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Registered: ‎11-24-2020

Hey,

Thanks for this, so basically this way its possible to detect when either is applied?

Thanks

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dharpeer
Adventurer
Adventurer
403 Views
Registered: ‎11-24-2020

Hey,

This was a tutorial on timing constraints priority.

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hongh
Moderator
Moderator
329 Views
Registered: ‎11-04-2010

Hi, @dharpeer ,

Yes, in this way, both clocks will detected and work in the design.

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View solution in original post

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

You said it was a xilinx one

can you post a link please, sounds interesting

 

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