06-19-2020 05:41 AM - edited 06-19-2020 06:03 AM
I have a "sync rst A" (belongs to clock domain A), coming from some IP with Clock domain A. Same for sync rst B.
Now, I want to use the AXI SMC, which both clock domains are passed into, and it has only 1 reset.
I thought to connect both synced resets into a logic AND and pass the output to the SMC input.
Both clock domains are async to each other and declared in XDC as async groups.
Nevertheless, in Reports - CDCS it gives a critical warning for CDC-10, saying that it is a "combinational logic before a synchronizer", which is correct....
Any idea how do I solve this issue?
Should I waive this warning (does Waive means the tool actually treats it as false path?)
Or any other logic solution?
06-19-2020 09:36 AM
It seems like your system does not have any proper CDC.
Simply using async groups does not properly handle CDC design and is actually a bad idea when there is CDC between those two groups. The proper IPs for CDC will either auto-generate the proper constraints or the documentation/example design will tell you what constraints you need to add. Having async clock groups would overrule those IP constraints.
By SMC do you mean the SmartConnect IP or some other IP? I don't see any IP that Xilinx refers to SMC, maybe a typo of EMC?
For reset it seems somewhat unusual that reset be generated by AXI IPs. Are you sure your reset generation design is correct? See this note from the SmartConnect docs
SmartConnect does not support independent reset domains. If any master or slave device
connected to SmartConnect is reset, then all connected devices must be reset concurrently.
If you really do want to use both resets in a separate clock domain you need to synchronize both into that clock domain independently then combine them. The only Xilinx IPI core that I am aware of that does reset synchronization is the "processor system reset"... you can also use the XPM_CDC_ASYNC_RST or XPM_CDC_SYNC_RST in RTL.