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prophet36
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Registered: ‎08-13-2011

Multiple timing groups, each with different OFFSET OUT constraints

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I'm in the process of learning about timing constraints. I'm trying to create two timing groups, one for the connections to a Cypress FX2LP and another for the connections to an SDRAM.


Here is the .ucf file and here is a grep of the timing report (I told it to give me all paths, not just the top/bottom three).


Why is the ram_grp OFFSET OUT constraint applied to fx2Data_io<*>, when those signals are in fx2_grp? Why are none of the actual ram_grp signals constrained?


Similarly, why is the fx2_grp OFFSET OUT constraint applied to ramAddr_out<*>, when those signals are actually in ram_grp?


Also, why does fx2Data_io<*> appear under both constraints, but ramData_io<*> appears under neither?


I'm obviously specifying the groups or the constraints incorrectly, but I can't see how.


Tools: ISE 14.1 P.15xf on lin64
FPGA: xc3s200an-4-ftg256


Chris

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avrumw
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Guide
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Registered: ‎01-23-2009

Ah. Sorry...

 

Here's the problem (although the TNM should still be used).

 

The OFFSET OUT command accepts two sets of TIMEGROUPs - one before the keyword OFFSET and one at the end of the command. The first specifies the group of pads, the seconds tells the tool the group of clocked elements inside the design that can be the startpoints of those paths. You are using the wrong one.

 

TIMEGRP ram_grp OFFSET = OUT 10 ns AFTER "fx2Clk_in";
TIMEGRP fx2_grp OFFSET = OUT 15 ns AFTER "fx2Clk_in";

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

The problem is your use of the TNM_NET command instead of the TNM command. The (only) difference between these two commands is how they act on primary inputs; the TNM command puts the top level port (pad) of the design in the group, the TNM_NET command propagates through the IBUF and reaches all clocked elements combinatorially reachable from the top level port.

 

In general the TNM_NET command should be used on the clock input for creating the group for a PERIOD constraint (which you want applied to all clocked elements reachable from the clock input), and the TNM command for creating pad groups.

 

Avrum

prophet36
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Registered: ‎08-13-2011

Thanks for your reply Avrum. I tried TNM originally but it failed to apply the constraint to anything at all. Here's the new .ucf file. The result is:


WARNING:Timing:3224 - The clock fx2Clk_in associated with OFFSET = OUT 10 ns
AFTER COMP "fx2Clk_in" TIMEGRP ram_grp; does not clock any registered output
components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 10 ns AFTER COMP
"fx2Clk_in" TIMEGRP ram_grp; ignored during timing analysis
WARNING:Timing:3224 - The clock fx2Clk_in associated with OFFSET = OUT 15 ns
AFTER COMP "fx2Clk_in" TIMEGRP fx2_grp; does not clock any registered output
components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 15 ns AFTER COMP
"fx2Clk_in" TIMEGRP fx2_grp; ignored during timing analysis


Also, I'm confused that your answer talks about primary inputs and IBUFs. My understanding of the OFFSET OUT constraints (which I'm focusing on) is that they say nothing about inputs; they place an upper limit on the time between a transition at the input clock pad and a transition of each output pad caused by the clock transition.


If it's useful, for reference, here's the actual memory controller VHDL. This module is instantiated at the top level alongside a 1:1 clock generator DLL which drives all internal logic and the ramClk_out pin using a FDDRCPE block.


- Chris

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

Ah. Sorry...

 

Here's the problem (although the TNM should still be used).

 

The OFFSET OUT command accepts two sets of TIMEGROUPs - one before the keyword OFFSET and one at the end of the command. The first specifies the group of pads, the seconds tells the tool the group of clocked elements inside the design that can be the startpoints of those paths. You are using the wrong one.

 

TIMEGRP ram_grp OFFSET = OUT 10 ns AFTER "fx2Clk_in";
TIMEGRP fx2_grp OFFSET = OUT 15 ns AFTER "fx2Clk_in";

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vemulad
Xilinx Employee
Xilinx Employee
8,731 Views
Registered: ‎09-20-2012

Hi Chris,

 

I agree with Avrum on the usage of TNM instead of TNM_NET.

 

If the net names which you mention in the TNM_NET group constraint are output ports then it does not make any difference in using TNM or TNM_NET. How ever if these are input or inout signals then it makes a difference.

 

For better understanding you can generate the timing group section in the timing analysis and compare the one with TNM and with TNM_NET. To generate time group section follow the steps below:

1. In ISE GUI, double click on  "Analyze Post-Place and Route Static timing" under place and route process.

2. Now go to Timing --> Run analysis in menu bar.

3. This directs you to "Run Timing Analysis" dialog box where you need to check "Time group section" in Report options tab and click on OK.

 

Also regarding the new warning messages you are reciveing, modify the OFFSET OUT constraint as below in the UCF and check if the issue persists.

 

TIMEGRP ram_grp OFFSET = OUT 10 ns AFTER "fx2Clk_in" ;
TIMEGRP fx2_grp OFFSET = OUT 15 ns AFTER "fx2Clk_in" ;

 

Thanks,

Deepika.

 

 

Thanks,
Deepika.
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prophet36
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Registered: ‎08-13-2011

Great, thanks guys. I understand the syntax now.

 

Chris

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