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Visitor leonardlopes
Visitor
358 Views
Registered: ‎09-11-2018

My UART module wants double the clock rate

Hello,

I'm experimenting with FPGAs and I created a simple UART module for my ICEStick that sends and receives data at full duplex.

In my experiment I created a python script that sends data to my UART module via serial interface (using pyserial) and the FPGA just transmits it back after receiving it.

It actually works, but the weird thing is that I provide double the clock pulse that I have computed I should provide to the UART module

For a connection rate of 115200 BAUD I computed that I would need to divide the clock rate by 12Mhz / 115200 = 104 (being 12Mhz the clock of the ICEStick clock generator)

If do that I lose a lot of character during transmission. If I divide by 52 though then everything works smoothly and all the characters come and go flawlessly

I checked in simulation that the divided clock is actually of the expected period (~8us).

Does anybody have an idea on what could be going on?

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1 Reply
Explorer
Explorer
145 Views
Registered: ‎07-18-2018

Re: My UART module wants double the clock rate

Hi leonardlopes,

ICEStickisn't a Xilinx part, and I don't know very much about it or the tools. But if this was on a Xilinx FPGA part, i would ask to see the Timing Simulation of the UART module with example data.

The UART module is suppose to be asynchronous, so it would be interesting to know if the reason it works when double the frequency you are using is because you are double sampling and therefore able to catch all the transitions (and possibly see your UART HDL description)

Additionally it might be the python transmits script is incorrect. A scope would be a great way to test what the UART signal coming from the script looks like and that it has the right baud rate.

Again, this isn't a Xilinx part, so I can't really provide further ideas.

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