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raspecht
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Registered: ‎01-24-2012

NET vs INST

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I inherited a design that is not bad, but I wouldn’t call it “organized” or “methodical”.  In the constraints file, the author keeps using “inst” and “net” almost interchangeably.    I did do quite a bit of searching and reading of the UG612 document to see when each is appropriate, but I haven’t found a unified reasoning.    Simple example is below and I cannot figure out why NET was used in one case and INST in the next the signals are fundamentally the same (at least logic wise).

 

NET “ADDR[*]"   TNM = "ADDR_T";

INST “DATA[*]"   TNM = "DATA_T”;

 

Can somebody explain to me the appropriate use cases of INST and NET.  I think that might help me quite a bit.

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gszakacs
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Registered: ‎08-14-2007

An instance refers to a physical block in the FPGA like a LUT, flip-flop, slice, or pad.  In many cases

the name of the instance is derived from the name of the net it drives.  In all cases a pad net has

the same name as the pad instance.  That is probably why you don't get errors from the mix

of INST and NET for the FPGA pin names.  For TNM, an INST is traced forward to the nets it

drives.  Again in the case of a pad, this means that using the pad instance traces forward to

the pad net, so the two forms are equivalent.

 

Hope this helps,

 

Gabor

-- Gabor

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gszakacs
Professor
Professor
6,803 Views
Registered: ‎08-14-2007

An instance refers to a physical block in the FPGA like a LUT, flip-flop, slice, or pad.  In many cases

the name of the instance is derived from the name of the net it drives.  In all cases a pad net has

the same name as the pad instance.  That is probably why you don't get errors from the mix

of INST and NET for the FPGA pin names.  For TNM, an INST is traced forward to the nets it

drives.  Again in the case of a pad, this means that using the pad instance traces forward to

the pad net, so the two forms are equivalent.

 

Hope this helps,

 

Gabor

-- Gabor

View solution in original post

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raspecht
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Registered: ‎01-24-2012

Thanks.   That does clarify things quite a bit and match up to my research.  I was just a bit confused as to the blatant lack of consistent approach on their choices and thought I was missing something.  I did build the design both ways (with INST and NET) and the result was “exactly” the same.

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limab_erik
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Registered: ‎02-10-2009

I have a similar question:

 

What is the difference in using the PIN keyword rather then INST when adding FPGA IO-pins to a timing group (later used in OFFSET constratints)?

 

Example:

What is the difference between

PIN "pu_data(*)" TNM = pu_bus_in;

INST "pu_data(*)" TNM = pu_bus_in;

(pu_data(*) is my bi-derectional data-bus to an FPGA-external chip)

 

The question arised when I played around with the designpreservation flow. It seems as bi-directional busses can not be grouped with the INST keyword when using a bottom up synthesis flow. Moving over to using PIN solved the problem. When anlyzing the constrainted path with PlanAhead it seems as it does not make any difference.

 

Ceers

/Erik

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