UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer heber.green
Observer
7,617 Views
Registered: ‎03-18-2009

Necessity of OFFSET_IN constraints for DDR registers?

Hello,

 

Can anyone clarify for me why the offset_in constraint is required for a DDR register? My understanding is that there is a known delay from the pad to the DDR register, and then the output of the DDR register to whatever the next register is could be covered under a period constraint. 

 

 

If I add an offset in constraint, is it having any effect other than reporting the known delay between the pad and the DDR register itself?

 

Thanks,

-Heber

0 Kudos
1 Reply
Guide avrumw
Guide
7,614 Views
Registered: ‎01-23-2009

Re: Necessity of OFFSET_IN constraints for DDR registers?

You are pretty much correct.

 

Since the IDDR is in the IOB, and assuming you are using a "normal" clocking mechanism (i.e. a global, regional, or I/O clock), then the timing of the input is fixed. Therefore, the constraint won't have any effect on the placement, routing, or any other attributes of the cells.

 

However, there is nothing that states that this "fixed" timing is correct for the interface you are trying to design. Remember (and this is a cardinal rule) your constraints are there to describe the system outside the FPGA to the static timing analysis tools. In some cases, this has the effect of influencing the placment or routing of the design... just not in this case.

 

If you correctly constrain your inputs (that use IDDRs), you will get a timing report for those inputs. If they pass, this is a statement that your chosen input structure meets the requirements imposed by your system.

 

If the constraint fails, it lets you know that you need to do something to fix it. This could be something like adding an IDELAY (or changing its value), or modifying the phase of an internal clock (i.e. using the phase shift of the MMCM).

 

Avrum