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subhban15
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Registered: ‎07-12-2016

Need for Recovery and Removal times for asynchronous reset in flip-flops? Can they have a negative value?

The way a flipflop can have a negative hold time, can they have negative removal/recovery time too?

Could anyone kindly elaborate, what all factors in the design can sum up their value (the way setup time involves the time needed to switch the pass-transistors or charge up the capacitors of the inverters and hold time is negative or positive depending on the switching time of the pass-transistor). I understand that the delays or time requirements will be completely design-based, but it would be easy for me (and for other students in the field) to understand if one could explain using a very basic internal diagram for flip-flop with asynchronous reset.

 

Thank you for sparing your precious time :) :)

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austin
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Registered: ‎02-27-2008

s,

 

Xilinx designs the circuits to work, so you don't have to.

 

If anyone is interested in how we design FPGA devices, I invite you to look at our patents.

 

The purpose of the forums is not to teach you how to design a FPGA, but to help you use them.

 

Plenty of ASIC design courses on line, but not here.

Austin Lesea
Principal Engineer
Xilinx San Jose
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markcurry
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Registered: ‎09-16-2009


@subhban15 wrote:

The way a flipflop can have a negative hold time, can they have negative removal/recovery time too?

 

 

 


 

I don't see why one couldn't have a negative removal/recovery, just like a negative setup/hold time.

Here's how I think about it - note that this is a mental exercise with little basis in reality - I've no knowledge nor experience in how Xilinx (or any other vendor for that matter) designs their low-level FF circuits.

 

My thoughts are like this - draw a flip flop symbol with all the ports.  Inside the cell ports add a "virtual" buffer on all I/O.  This virtual buffer is just to mentally repsresent delay.  For normal setup/hold timing, just focus on the delay values for the "clk" pin, and "d" pin.  Assume a few different cases where one "buffer" or the other has significant more delay than the other.  You can quickly sketch out examples for when one might see a negative setup or hold time.

 

Now as to removal/recovery - it's the same idea, but focus on the "clk" and async reset port of the flop.  Same analysis/idea applies right?

 

Again, to repeat this sort of mental exercise has little basis in the actual underlying circuit, but I think the analysis is valid.

 

(waiting for someone else to point out some obvious error, but oh well...)

 

--Mark