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Visitor sbobbili
Visitor

Need help to provide timing constraints between FPGAs after CPM

We are trying to add constraints after CPM between FPGAs, want to get defined delay between PADs <--> REGs 

We are using Virtex 5 FPGA  and trying to add constraints in UCF file.

 

There are receive and send ports in both the FPGAs 

We are using two clocks CCLK - normal functionality, FCLK- for CPM

 

Give the some example constrains to use in our case.

 

Regards,

Sarath 

 

 

 

 

 

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3 Replies
Scholar dpaul24
Scholar

Re: Need help to provide timing constraints between FPGAs after CPM

@sbobbili,

 

Give the some example constrains to use in our case.

Sorry your problem description is not clear to me.

 

Generic help in constraining-

Read this docu for Virtex5 : https://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf

 

This should also be helpful:

https://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594

 

 

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FPGA enthusiast!
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Moderator
Moderator

Re: Need help to provide timing constraints between FPGAs after CPM

Hi Sarath,

To understand more about constraints and what constraints are needed refer UG612. This UG has details about all the timing constraints and their use cases.

Also after going through UG612 and CGD (mentioned in above post) if you have any questions regarding specific constraints feel free to post here.

Thanks,
Yash
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Visitor sbobbili
Visitor

Re: Need help to provide timing constraints between FPGAs after CPM

Hi Yash,

 

Thanks for the information.

 

Because of area issue, we need to split the design between two FPGAs.

Need to use CPM because of limited traces between FPGAs

 

I am attaching sample code and constraints used on both FPGAs, please go through it let me know I am missing any thing

 

Regards,

Sarath

 

 

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