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Visitor strauman
Visitor
2,798 Views
Registered: ‎01-23-2017

Need help understanding hold violation

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I'm analyzing a timing report (attached) with hold violations. Looking at the first of these violations: the source and destination clocks originate at the same MMCM (OUT0 and OUT1, respectively, with OUT1 providing half the rate of OUT0). What I don't understand is that all the delays from the master clock upstream of the MMCM up to the clock input of the MMCM (MMCME3_ADV_X0Y4) are budgeted *differently* in the source and destination clock paths. E.g., the net 'U_App/U_Reg/U_SimJesdClock/lopt' adds 1.344ns in the source clock path but 1.533ns in the destination clock path. I would assume that the static delay of this net should contribute the same delay to both outputs of the MMCM, i.e., essentially cancel out. Why does it not?

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Xilinx Employee
Xilinx Employee
5,105 Views
Registered: ‎05-14-2008

Re: Need help understanding hold violation

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The basic default worst case methodology for hold analysis is to calculate the min delay for source clock path and max delay for destination clock path. So this hold path first follows the default analysis. 

And yes, you're right. The common part of the source/destination clock paths should not contribute different delay values. So we take into account a "clock pessimism removal" in the equation to remove the pessimism part brought by the min/max delay calculation of the common clock path.

The "clock pessimism removal" is listed at the end of the path analysis.

 

-Vivian

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Xilinx Employee
Xilinx Employee
5,106 Views
Registered: ‎05-14-2008

Re: Need help understanding hold violation

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The basic default worst case methodology for hold analysis is to calculate the min delay for source clock path and max delay for destination clock path. So this hold path first follows the default analysis. 

And yes, you're right. The common part of the source/destination clock paths should not contribute different delay values. So we take into account a "clock pessimism removal" in the equation to remove the pessimism part brought by the min/max delay calculation of the common clock path.

The "clock pessimism removal" is listed at the end of the path analysis.

 

-Vivian

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Historian
Historian
2,763 Views
Registered: ‎01-23-2009

Re: Need help understanding hold violation

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There is some more discussion of clock pessimism in this post.

 

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