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rkfournier
Adventurer
Adventurer
956 Views
Registered: ‎05-09-2018

Need ideas for resolving pesky hold violations

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I have an Artix-7 design where Implementation consistently results in hold violations on three end-points within a single clock domain. The worst case violation is -0.262ns and the total is -0.786ns. I have already found and tried the ExploreWithAggressiveHoldFix Physical Optimization option, which had no effect.

What else should I try?

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rkfournier
Adventurer
Adventurer
875 Views
Registered: ‎05-09-2018

Hi Avrum,

   I just stumbled on a mistake in my logic where the clock was also being used as the reset within a VHDL process. The three points that failed were the three registers affected by this mistake. It was identified in the Synthesis warnings which I had missed. Once this mistake was corrected the design met all timing.

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3 Replies
947 Views
Registered: ‎11-26-2018

Hello RK,

-retiming option during synthesis?

Guy

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avrumw
Expert
Expert
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Registered: ‎01-23-2009

in hold violations on three end-points within a single clock domain

That is extremely unusual. Hold times within the same domain are generally limited by the fact that the clock skew is constrained, and since the clock skew is relatively small, the tool almost never has problems fixing them.

Violations of 0.25ns after the tool has done it's best to fix them don't really make sense...

Can you post one of the failing paths - the complete timing report, including the source clock delay and destination clock delay. Even if the startpoint and endpoint are on the same static timing analysis clock (as reported by the tool), you can still have structurally different clock insertion paths which can cause unusual skew (and hence hold violations).

Avrum

rkfournier
Adventurer
Adventurer
876 Views
Registered: ‎05-09-2018

Hi Avrum,

   I just stumbled on a mistake in my logic where the clock was also being used as the reset within a VHDL process. The three points that failed were the three registers affected by this mistake. It was identified in the Synthesis warnings which I had missed. Once this mistake was corrected the design met all timing.

View solution in original post

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