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dschussheim
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Explorer
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Registered: ‎06-08-2017

Negative slack in design with "many" logic levels

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I have a design that fails to meet timing. It says it has 50 levels of logic. Are there any good strategies to get this to meet timing? Is it just a poorly written module, or are there other implementation strategies that can help? What is the approach for timing closure in this sort of situation? I attached the timing report for the worst path.

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avrumw
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Expert
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Registered: ‎01-23-2009

Yes, this is just bad coding. You have an huge combinatorial path that goes through at least four addition/subtraction operations (with one being at least 40 bits wide) and 14 LUTs. This is WAY too much logic for a path running at 100MHz. 

You need to redesign this completely. You need to investigate how to pipeline this path to break the logic over at least two pipeline stages.

While tool options can improve timing, they can maybe make a 5%-10% difference (at best) - this is not going to be solved by tool options.

Avrum

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avrumw
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Expert
215 Views
Registered: ‎01-23-2009

Yes, this is just bad coding. You have an huge combinatorial path that goes through at least four addition/subtraction operations (with one being at least 40 bits wide) and 14 LUTs. This is WAY too much logic for a path running at 100MHz. 

You need to redesign this completely. You need to investigate how to pipeline this path to break the logic over at least two pipeline stages.

While tool options can improve timing, they can maybe make a 5%-10% difference (at best) - this is not going to be solved by tool options.

Avrum

View solution in original post

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