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Visitor
Visitor
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Registered: ‎10-28-2018

New clock constraint required when clock net changes name at module port?

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Is a new clock constraint required when a clock net changes name when entering a module port?  For example, if a clock net named 'system_clk' that enters the 'clock' port of a module, is a create_derived_clk constraint required?  Or does the timing analyzer confer the characteristics of 'system_clk' onto 'clock'?

For example:

module UserModule (

    input    wire clock,

    input    wire reset_n,

    output reg   sig

);

 

UserModule my_module (

    .clock     ( system_clk    ),       //  <=  is a new constraint needed for 'clock'

    .reset_n ( system_reset ),

    .sig        ( signal_out      )

)

 

Thanks!

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Teacher
Teacher
304 Views
Registered: ‎07-09-2009
No
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Teacher
Teacher
305 Views
Registered: ‎07-09-2009
No
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Visitor
Visitor
302 Views
Registered: ‎10-28-2018

 

Thanks.  Makes sense that a module entry name change shouldn't require a new constraint, but since I couldn't find it explicitly stated I thought I should ask.  

Much appreciated!

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