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Visitor
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Registered: ‎12-07-2015

New to CPLD programming: Need a timing explanation for code I inherited

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This if for the Xilinx CoolRunner II xc2c128-6vq100.

Before anyone asks, yes, I did try looking all of this up, but since I have never done this before the explanations were Greek to me.

I am typically a high-level language programmer, so I am having a difficult time with the hardware aspect of things. This is code I inherited and I don't feel comfortable changing things if I don't know what they are doing.

I have these 4 lines of code in my user constraints file:

 

NET "I_strobe_n" BUFG=CLK;

TIMESPEC TS_I_strobe_n = PERIOD "I_strobe_n" 220 ns LOW 20 ns;

OFFSET = IN  220 ns BEFORE I_strobe_n;

OFFSET = OUT 50 ns AFTER  I_strobe_n;   

 

I always get a warning saying : Constraint <TIMESPEC TS_I_strobe_n = PERIOD
   "I_strobe_n" 220 ns LOW 20 ns;> [filename.ucf()]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'I_strobe_n'.

 

If add "NET "I_strobe_n" TNM_NET = I_strobe_n;" to fix that Warning, then I get a new warning:

The Offset constraint <OFFSET = IN  220 ns BEFORE
   I_strobe_n;> [filename.ucf()], is specified without a duration.  This
   will result in a lack of hold time checks in timing reports.  If hold time
   checks are desired a duration value should be specified following the 'VALID'
   keyword.

 

I think a lot of my problem is that I don't understand what is going on here. If someone could explain those 4 lines of code, that would really help.

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Highlighted
Guide
Guide
16,567 Views
Registered: ‎01-23-2009

Re: New to CPLD programming: Need a timing explanation for code I inherited

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NET "I_strobe_n" BUFG=CLK;

 

I am actually not familiar with this one - I suspect it is specific to CPLDs (and I only do FPGAs). But I can speculate.

 

In the CPLD (like FPGAs) there are some dedicated resources for propagating the clock signal inside the CPLD. The clock has to be distributed to all clocked elements with bounded skew (the difference between the arrival at the nearest cell and the arrival at the farthest). These dedicated clock routes are driven by a dedicated clock buffer called a "BUFG" (a Global clock BUFfer) This line is telling the tool to use one of these dedicated clock networks for the signal called "I_strobe_n" in your design.

 

NET "I_strobe_n" TNM_NET = I_strobe_n;

 

This tells the tool to create a Time NaMe (or timegroup) named "I_strobe_n". Into this time group, it is to put all clocked elements in the design that are clocked by the signal named "I_strobe_n". In this case, the name of the timegroup (which is chosen by the person who wrote the constraints) is the same as the name of the net - most people do it this way, but it doesn't have to be. If you wanted to call the timegroup "george" then you would, instead do 

 

NET "I_strobe_n" TNM_NET = george;

 

In all the rest of my commands, I will use "george" as the name of the timegroup, so that you can tell if I am referring to the timegroup or the net.

 

TIMESPEC TS_I_strobe_n = PERIOD "george" 220 ns LOW 20 ns;

 

This is definint a TIMESPEC, which is a fancy word for a constraint. The constraints name is TS_I_strobe_n (all TIMESPECs must start with the letters TS). The type of TIMESPEC is a PERIOD constraint - this is defining the period of a clock. This period is applied to all clocked elements in the "george" timegroup. The period of the defined clocked is 220ns, it is active "LOW" (so the falling edge of the clock is used for all OFFSET constraints associated with this clock), and the low time is 20ns (so the high time is 200ns).

 

This basically tells the tool that it has a maximum of 220ns for propagation between any clocked element in group "george" to any other clocked element in group "george" (with some other factors like clock skew, jitter, and setup time included).

 

You definitely need the TNM_NET command before this, otherwise the group "george" (in your case I_strobe_n) doesn't exist, which is why you get the error without it.

 

OFFSET = IN  220 ns BEFORE I_strobe_n;

 

This defines the timing of all input signals to your design. It says "All inputs to the CPLD become valid 220ns before the active edge (in this case the falling edge) of the net I_strobe_n. (This is with respect to the pin of the CPLD, and has nothing to do with the Timegroup "I_strobe_n", which I call "george").

 

This has two problems

  - this basically says the input change way at the beginning of each clock cycle - an entire clock period before the active edge of the clock

       - that's improbable - any real device that is sharing a clock with this FPGA will need some time to generate its outputs - so the inputs will not be valid a full 220ns before the active edge of the clock

   - it has no VALID keyword, which tells the tool how long the signal remains valid after becoming valid

      - this is what the other message is telling you. Its not an error, its just a warning saying "This is unlikely"

 

A more meaningful one would be

 

OFFSET = IN 170ns VALID 170ns BEFORE I_strobe_n;

 

Which says that the inputs become valid 170ns before the active edge of the clock, and remain valid for 170ns (so right up to the clock). This basically means right after the clock, and for up to 50ns after that, the signal is invalid - it is in the process of changing from the old value to a new value.

 

OFFSET = OUT 50 ns AFTER  I_strobe_n;   

 

This is similar for the outputs. It is telling the tool, that you want all outputs of the CPLD to be valid no later than 50ns after the active edge of the clock arriving at the I_strobe_n input pin of the CPLD.

 

The PERIOD, OFFSET IN and OFFSET OUT define the timing requirements of your system. You are basically saying "if the CPLD can meet these constraints, then the CPLD will operate properly in my system". The tools will attempt to implement your code while keeping these constraints in mind. If the tools come up with an implementation that can meet these requirements, then it will say that you have "met all constraints". If it cannot, one or more of these constraints will fail, and the tools will tell you which ones it wasn't able to satisfy, and will give you some information as to why.

 

Avrum

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Highlighted
Guide
Guide
16,568 Views
Registered: ‎01-23-2009

Re: New to CPLD programming: Need a timing explanation for code I inherited

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NET "I_strobe_n" BUFG=CLK;

 

I am actually not familiar with this one - I suspect it is specific to CPLDs (and I only do FPGAs). But I can speculate.

 

In the CPLD (like FPGAs) there are some dedicated resources for propagating the clock signal inside the CPLD. The clock has to be distributed to all clocked elements with bounded skew (the difference between the arrival at the nearest cell and the arrival at the farthest). These dedicated clock routes are driven by a dedicated clock buffer called a "BUFG" (a Global clock BUFfer) This line is telling the tool to use one of these dedicated clock networks for the signal called "I_strobe_n" in your design.

 

NET "I_strobe_n" TNM_NET = I_strobe_n;

 

This tells the tool to create a Time NaMe (or timegroup) named "I_strobe_n". Into this time group, it is to put all clocked elements in the design that are clocked by the signal named "I_strobe_n". In this case, the name of the timegroup (which is chosen by the person who wrote the constraints) is the same as the name of the net - most people do it this way, but it doesn't have to be. If you wanted to call the timegroup "george" then you would, instead do 

 

NET "I_strobe_n" TNM_NET = george;

 

In all the rest of my commands, I will use "george" as the name of the timegroup, so that you can tell if I am referring to the timegroup or the net.

 

TIMESPEC TS_I_strobe_n = PERIOD "george" 220 ns LOW 20 ns;

 

This is definint a TIMESPEC, which is a fancy word for a constraint. The constraints name is TS_I_strobe_n (all TIMESPECs must start with the letters TS). The type of TIMESPEC is a PERIOD constraint - this is defining the period of a clock. This period is applied to all clocked elements in the "george" timegroup. The period of the defined clocked is 220ns, it is active "LOW" (so the falling edge of the clock is used for all OFFSET constraints associated with this clock), and the low time is 20ns (so the high time is 200ns).

 

This basically tells the tool that it has a maximum of 220ns for propagation between any clocked element in group "george" to any other clocked element in group "george" (with some other factors like clock skew, jitter, and setup time included).

 

You definitely need the TNM_NET command before this, otherwise the group "george" (in your case I_strobe_n) doesn't exist, which is why you get the error without it.

 

OFFSET = IN  220 ns BEFORE I_strobe_n;

 

This defines the timing of all input signals to your design. It says "All inputs to the CPLD become valid 220ns before the active edge (in this case the falling edge) of the net I_strobe_n. (This is with respect to the pin of the CPLD, and has nothing to do with the Timegroup "I_strobe_n", which I call "george").

 

This has two problems

  - this basically says the input change way at the beginning of each clock cycle - an entire clock period before the active edge of the clock

       - that's improbable - any real device that is sharing a clock with this FPGA will need some time to generate its outputs - so the inputs will not be valid a full 220ns before the active edge of the clock

   - it has no VALID keyword, which tells the tool how long the signal remains valid after becoming valid

      - this is what the other message is telling you. Its not an error, its just a warning saying "This is unlikely"

 

A more meaningful one would be

 

OFFSET = IN 170ns VALID 170ns BEFORE I_strobe_n;

 

Which says that the inputs become valid 170ns before the active edge of the clock, and remain valid for 170ns (so right up to the clock). This basically means right after the clock, and for up to 50ns after that, the signal is invalid - it is in the process of changing from the old value to a new value.

 

OFFSET = OUT 50 ns AFTER  I_strobe_n;   

 

This is similar for the outputs. It is telling the tool, that you want all outputs of the CPLD to be valid no later than 50ns after the active edge of the clock arriving at the I_strobe_n input pin of the CPLD.

 

The PERIOD, OFFSET IN and OFFSET OUT define the timing requirements of your system. You are basically saying "if the CPLD can meet these constraints, then the CPLD will operate properly in my system". The tools will attempt to implement your code while keeping these constraints in mind. If the tools come up with an implementation that can meet these requirements, then it will say that you have "met all constraints". If it cannot, one or more of these constraints will fail, and the tools will tell you which ones it wasn't able to satisfy, and will give you some information as to why.

 

Avrum

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Visitor
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Registered: ‎12-07-2015

Re: New to CPLD programming: Need a timing explanation for code I inherited

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Thank you so much! That is an even better explanation than I had hoped for!!

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