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Visitor
Visitor
895 Views
Registered: ‎02-22-2019

No Auto-derived clocks Clocking Wizard

I used the clock wizard to generate an MCMM with 4 output clocks. When I synthesize and implement the design (Vivado 2017.4), I dont see any auto-derived clocks. The input clock constraint is present in the generated IP constraint file by Vivado. report_clocks command does not list any auto-derived clocks either.

I have instantiated the component in my top entity (VHDL). But, I get a INFO message (not as error/warning):

  • [Vivado 12-5777] IP Instance 'clk_wiz_0' cannot be used in a module reference: The 'xilinx.com:ip:clk_wiz:5.4' core does not support module reference.

Could this be a problem? But, the MCMM is placed in the resources list. I dont understand what is the problem here. If anybody could help me understand what could have gone wrong.

 

 

 

 

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Teacher
Teacher
868 Views
Registered: ‎07-09-2009

you wont see any derived clocks in the xdc , they are automatic

as for the warning, does it simulate ok ?
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Moderator
Moderator
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Registered: ‎09-15-2016

Hi @kriven55 

report_clock does reports all the clocks in a design, including propagated clocks, generated and auto-generated clocks, virtual clocks, and inverted clocks.

For the warning  "[Vivado 12-5777] IP Instance 'clk_wiz_0' cannot be used in a module reference: The 'xilinx.com:ip:clk_wiz:5.4' core does not support module reference."

Please refer the below link which says clocking wizard IP is not supported for XCI referencing.

https://forums.xilinx.com/t5/Design-Tools-Others/clock-wiz-dose-not-support-module-reference-in-vivado/m-p/852545#M11955

Regards
Rohit
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Visitor
Visitor
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Registered: ‎02-22-2019

Hi,

I did not mean in the xdc. But in general, the clocks in the design. The MMCM/PLL clocks should be listed as derived clocks, which does not happen here.

I have not checked the simulation yet.

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Visitor
Visitor
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Registered: ‎02-22-2019


@thakurr wrote:

Hi @kriven55 

report_clock does reports all the clocks in a design, including propagated clocks, generated and auto-generated clocks, virtual clocks, and inverted clocks.

Yes, but this does not answer my question. What could have gone wrong? Could it be because the XCI referencing is not supported?

Why does Xilinx then offer a component instantiation file for it? Why complicate everything?

For the warning  "[Vivado 12-5777] IP Instance 'clk_wiz_0' cannot be used in a module reference: The 'xilinx.com:ip:clk_wiz:5.4' core does not support module reference."

Please refer the below link which says clocking wizard IP is not supported for XCI referencing.

https://forums.xilinx.com/t5/Design-Tools-Others/clock-wiz-dose-not-support-module-reference-in-vivado/m-p/852545#M11955


 

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