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Voyager
Voyager
521 Views
Registered: ‎05-30-2018

No common primary clock between related clocks

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Hello,

After applying this constraint:

create_clock -period 41.667 -name dfe_clk [get_ports dfe_clk]

I get this violation:

No common primary clock between related clocks
The clocks clk_out1_design_1_clk_wiz_1_0 and dfe_clk are related (timed together) but they have no common primary clock.
The design could fail in hardware.
To find a timing path between these clocks, run the following command:
report_timing -from [get_clocks clk_out1_design_1_clk_wiz_1_0] -to [get_clocks dfe_clk]

Here is fragment of related schematic:

fragment_of_diagram.png

 

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Xilinx Employee
Xilinx Employee
484 Views
Registered: ‎05-14-2008

Re: No common primary clock between related clocks

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From your schematic, I see that dfe_clk is driving not only the PLL but also the other logics. What are the other loads of dfe_clk? What is the coding like between dfe_clk port to the PLL and the other loads in your source file?

When you choose "single-ended capable clock", the PLL input needs to be connected to the clock port directly and the clock port is expected to not having any other loads except the PLL. The PLL IP contains the IBUF instance for the clock port. 

But in your case, the clock port is driving other loads besides the PLL, then in general you need to choose "Globle Buffer" or "No Buffer" so that the PLL IP does not contain the IBUF instantce. Otherwise, you'll have incorrect buffer connecting or constraints issue like you're having now.

-vivian

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9 Replies
Xilinx Employee
Xilinx Employee
513 Views
Registered: ‎05-14-2008

Re: No common primary clock between related clocks

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Can you run "report_clocks" and post the result?

This may be due to some conflict between your create_clock constraint and the constraint in the clocking wizard IP XDC.

There is a "clock source" pull-down list option in the clocking wizard IP custermization GUI. What did you choose for this option?

-vivian

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Voyager
Voyager
501 Views
Registered: ‎05-30-2018

Re: No common primary clock between related clocks

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Clock Report


Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode

Clock Period(ns) Waveform(ns) Attributes Sources
design_1_i/clk_wiz_0/inst/clk_in1 41.667 {0.000 20.833} P {design_1_i/clk_wiz_0/inst/clk_in1}
clkfbout_design_1_clk_wiz_1_0 41.667 {0.000 20.833} P,G,A {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT}
clk_out1_design_1_clk_wiz_1_0 16.667 {0.000 8.333} P,G,A {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0}
dfe_clk 41.667 {0.000 20.833} P {dfe_clk}
clk_spi 50.000 {0.000 25.000} P {i_spis_sck}


====================================================
Generated Clocks
====================================================

Generated Clock : clkfbout_design_1_clk_wiz_1_0
Master Source : design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
Master Clock : design_1_i/clk_wiz_0/inst/clk_in1
Multiply By : 1
Generated Sources : {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT}

Generated Clock : clk_out1_design_1_clk_wiz_1_0
Master Source : design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
Master Clock : design_1_i/clk_wiz_0/inst/clk_in1
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 -12.500 -25.000}
Generated Sources : {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0}

There is a "clock source" pull-down list option in the clocking wizard IP custermization GUI. What did you choose for this option?

Single-ended clock capable pin

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Voyager
Voyager
495 Views
Registered: ‎05-30-2018

Re: No common primary clock between related clocks

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I commented

create_clock -period 41.667 -name dfe_clk [get_ports dfe_clk]

and now it's  Ok.

So, the  clock input to PLL doesn't need to be constrained ?

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Voyager
Voyager
488 Views
Registered: ‎05-30-2018

Re: No common primary clock between related clocks

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I rushed a bit with my previous message: commenting creating clock for dfe_clk provokes huge number of "no clock" violations

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Xilinx Employee
Xilinx Employee
485 Views
Registered: ‎05-14-2008

Re: No common primary clock between related clocks

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From your schematic, I see that dfe_clk is driving not only the PLL but also the other logics. What are the other loads of dfe_clk? What is the coding like between dfe_clk port to the PLL and the other loads in your source file?

When you choose "single-ended capable clock", the PLL input needs to be connected to the clock port directly and the clock port is expected to not having any other loads except the PLL. The PLL IP contains the IBUF instance for the clock port. 

But in your case, the clock port is driving other loads besides the PLL, then in general you need to choose "Globle Buffer" or "No Buffer" so that the PLL IP does not contain the IBUF instantce. Otherwise, you'll have incorrect buffer connecting or constraints issue like you're having now.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
480 Views
Registered: ‎05-14-2008

Re: No common primary clock between related clocks

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If you set the PLL IP correctly, the create_clock constraint in the PLL IP XDC file (the constraint that creates "design_1_i/clk_wiz_0/inst/clk_in1" clock in your case) will be applied to the bfe_clk port automatically with a clock name "bfe_clk" in general. 

It is recommended that user add the clock constraint for top level clock port explicitly in user XDC. And the user create_clock constraint will overwrite the one in the PLL IP XDC because they're applying to the same object (the bfe_clk port).

However, because you're having the issue with the PLL IP setting I mentioned above, the create_clock in the IP XDC is not propagated to the bfe_clk port but just at the input pin of the PLL. And that results in the problem.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Voyager
Voyager
473 Views
Registered: ‎05-30-2018

Re: No common primary clock between related clocks

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Once Input clock "Source" option changed to "Global buffer", the issue disappered.

Thanks.

P.S. BTW have you any comment concerning disabling certain settings (e.g. "Clocking features" on "Clocking Option" tab and "Requested Output Frequency" on "OutputClocks" tab once "Allow Override Mode" is checked on "PLLE2 Settings" tab). Moreover when uncheck "Allow Override Mode", the disabled features become again editable but in reaality not: next opening of Clock Wizard settings show that old values are kept. The only way I found to circuvent this annoying issue is create new Clock Wizard with updated parameters, make connections then remove old Clock Wizard. I creted a post on this issue, but it still renains without solution.

Thanks once more

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Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎05-14-2008

Re: No common primary clock between related clocks

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I'm afraid "Global Buffer" is still not the correct option.

When you choose "Global Buffer", the PLL IP will contain a BUFG for the PLL input clock.

But your clock pad is driving some other logics outside the PLL. Usually a clock signal goes through a BUFG before it drives the clock pins of sequential cells.

If you have the BUFG inside the PLL IP, then you either don't have a BUFG for the other sequential loads, or you have two BUFG in parallel which is redundent. redundant.

The correct way would be to choose "No Buffer" and manually instantiate a BUFG for this clock net before it goes to the PLL or any other sequential loads.

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Xilinx Employee
Xilinx Employee
457 Views
Registered: ‎05-14-2008

Re: No common primary clock between related clocks

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@pavel_47 wrote:

BTW have you any comment concerning disabling certain settings (e.g. "Clocking features" on "Clocking Option" tab and "Requested Output Frequency" on "OutputClocks" tab once "Allow Override Mode" is checked on "PLLE2 Settings" tab). Moreover when uncheck "Allow Override Mode", the disabled features become again editable but in reaality not: next opening of Clock Wizard settings show that old values are kept. The only way I found to circuvent this annoying issue is create new Clock Wizard with updated parameters, make connections then remove old Clock Wizard. I creted a post on this issue, but it still renains without solution.

 


Why do you want to disable those settings? I don't quite understand your expectation.

BTW, the "Allow Override Mode" only controls the settings on PLLE2 Settings tab. 

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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