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Explorer
Explorer
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Registered: ‎05-31-2017

Non periodic signal as clock source : Error

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Hello everybody!

 

I'm back with new trouble!

 

I am now with the timing constraints. First time...

I can't find the good answer to my problem :

 

A module (including a MIG) generate an output signal used as input clock of a counter (increment every rising edge).

This signal, used as clock, isn't a clock! Sometimes it can be low during multiples seconds.

So, the timing report say "No clock".

 

Is there a way to ignore timing constraint s in this case, or my code is very very bad :) ?

 

Thanks

 

Paul

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Guide
Guide
4,135 Views
Registered: ‎01-23-2009

or my code is very very bad :) ?

 

Yes. It is.

 

In synchronous digital design (particularly in FPGAs) we don't do this.

 

If you want to increment a counter on a rising edge of an aperiodic signal, then you:

  - sample the aperiodic signal on a "fast enough" clock

     - this needs to use a synchronizer to ensure the signal is not metastable

     - this will also need a timing exception

  - use the synchronized version of the signal to determine when it has transitioned from a 0 to a 1

     - it it was a 0 on the last clock cycle, and is a 1 on this clock cycle then it experienced a rising edge

  - run the counter on the same high speed clock as the synchronizer

     - increment it on the clock cycle where the 0->1 transition was detected

 

Now your entire system runs on a single clock. If you specify a create_clock for that clock input, your design will be timed correctly.

 

Avrum

View solution in original post

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Highlighted
Guide
Guide
4,136 Views
Registered: ‎01-23-2009

or my code is very very bad :) ?

 

Yes. It is.

 

In synchronous digital design (particularly in FPGAs) we don't do this.

 

If you want to increment a counter on a rising edge of an aperiodic signal, then you:

  - sample the aperiodic signal on a "fast enough" clock

     - this needs to use a synchronizer to ensure the signal is not metastable

     - this will also need a timing exception

  - use the synchronized version of the signal to determine when it has transitioned from a 0 to a 1

     - it it was a 0 on the last clock cycle, and is a 1 on this clock cycle then it experienced a rising edge

  - run the counter on the same high speed clock as the synchronizer

     - increment it on the clock cycle where the 0->1 transition was detected

 

Now your entire system runs on a single clock. If you specify a create_clock for that clock input, your design will be timed correctly.

 

Avrum

View solution in original post

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Explorer
Explorer
2,187 Views
Registered: ‎05-31-2017

Hi @avrumw

 

Thank you for you answer.

 

It was the solution i wanted to avoid :) But it's the only good solution so... I will correct it!

 

 

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