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Observer
Observer
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Registered: ‎01-13-2010

OFFSET IN Reference

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In the block diagram below, how would I constrain the ADC data input OFFSET IN? Would it reference CLK1 and the tools figure the rest out, or do I need to explicitly create an OFFSET IN for the CLK2? The design works, I'm just trying to clean things up. right now, it's an OFFSET IN for CLK1

 

PS. Apologies if dupe post. The last one seemed to just disappear. 

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Guide
Guide
6,072 Views
Registered: ‎01-23-2009

Unfortunately, ISE is basically completely incapable of meaningfully performing timing analysis of this kind of interface.

 

You can start by looking at this post on SRAM interfaces - the read path of an external SRAM has the same characteristics as your path.

 

If, however, you are trying to do this in one clock, then it's going to be very difficult; constraints aren't going to help.

 

To start with, you should implement the ODDR for the forwarded clock. If you do timing analysis on this (the datasheet report), you will be able to get the maximum propagation delay from CLK1 to your forwarded clock. The tools will give you the maximum, but (I am pretty sure) not the minimum. You will have to make a guess for that, which isn't easy to do...

 

The minimum of a pure propagation path (given its maximum) can often be estimated with the 3:1 "rule of thumb" - the MIN propagation delay is 1/3 of the MAX propagation delay. However, the DCM messes this up - it is cancelling part of the insertion delay, so you can't just take off 2/3 of the number it reports. The "best" you can do is look at the full timing report (at max delays) and subtract off 2/3 of the delay through the ODDR and OBUF (and maybe a bit more for the rest of the stuff) - the IBUF and BUFG are cancelled by the DCM, and hence should be a constant over process/voltage/temperature (PVT). Note - depending on the DCM configuration, the resulting MIN delay estimate can be (and even meaningfully can be be) negative.

 

Using this, then adding the trace delays and the CLK->D of your ADC, you will be able to know the arrival time of the return data with respect to CLK1. Now you can write your OFFSET IN constraint with respect to CLK1...

 

One final note - it is generally a bad idea to clock an ADC with a clock generated by an FPGA (particularly using a DCM). The DCM has relatively high jitter on its output clocks (including some fairly nasty step discontinuities in phase). These will negatively affect the accuracy of the ADC sampling. It is always best to give the "cleanest possible" clock to an ADC (i.e. directly from an oscillator or high quality VCXO)...

 

Avrum

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Xilinx Employee
Xilinx Employee
3,464 Views
Registered: ‎05-14-2008

The clock used in OFFSET IN constraint should be an input clock to the FPGA but not an internal clock.

So it should be CLK1.

The tool "knows" the clock path inside the FPGA and will take care of that part.

 

Thanks

Vivian

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Highlighted
Guide
Guide
6,073 Views
Registered: ‎01-23-2009

Unfortunately, ISE is basically completely incapable of meaningfully performing timing analysis of this kind of interface.

 

You can start by looking at this post on SRAM interfaces - the read path of an external SRAM has the same characteristics as your path.

 

If, however, you are trying to do this in one clock, then it's going to be very difficult; constraints aren't going to help.

 

To start with, you should implement the ODDR for the forwarded clock. If you do timing analysis on this (the datasheet report), you will be able to get the maximum propagation delay from CLK1 to your forwarded clock. The tools will give you the maximum, but (I am pretty sure) not the minimum. You will have to make a guess for that, which isn't easy to do...

 

The minimum of a pure propagation path (given its maximum) can often be estimated with the 3:1 "rule of thumb" - the MIN propagation delay is 1/3 of the MAX propagation delay. However, the DCM messes this up - it is cancelling part of the insertion delay, so you can't just take off 2/3 of the number it reports. The "best" you can do is look at the full timing report (at max delays) and subtract off 2/3 of the delay through the ODDR and OBUF (and maybe a bit more for the rest of the stuff) - the IBUF and BUFG are cancelled by the DCM, and hence should be a constant over process/voltage/temperature (PVT). Note - depending on the DCM configuration, the resulting MIN delay estimate can be (and even meaningfully can be be) negative.

 

Using this, then adding the trace delays and the CLK->D of your ADC, you will be able to know the arrival time of the return data with respect to CLK1. Now you can write your OFFSET IN constraint with respect to CLK1...

 

One final note - it is generally a bad idea to clock an ADC with a clock generated by an FPGA (particularly using a DCM). The DCM has relatively high jitter on its output clocks (including some fairly nasty step discontinuities in phase). These will negatively affect the accuracy of the ADC sampling. It is always best to give the "cleanest possible" clock to an ADC (i.e. directly from an oscillator or high quality VCXO)...

 

Avrum

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