01-30-2009 02:28 AM
we need your support to set our timing constraints. As shown in this picture we have to drive a DEV by a DEV_CLK which is generated from the FPGA. The DEV Interface enable has also the same period of DEV_CLK. We tried to use these command lines in according with timing temporization:
NET "FEEDBACK" TNM_NET = "FEEDBACK";
TIMESPEC "TS_FEEDBACK" = PERIOD "FEEDBACK" 20 ns HIGH 10 ns;
TIMEGRP "DEV_in" OFFSET = IN 19 ns AFTER "DEV_CLK";
TIMEGRP "DEV_out" OFFSET = OUT 4 ns BEFORE "DEV_CLK"
TIMESPEC "TS_DEV" = FROM "DEV_IN" TO "DEV_IN": FEEDBACK*2;
The problem is that ISE couldn't accept the OFFSET command through an output clock signal and ignored a TIMESPEC command like that.
So, which is the right technique to set these kind of timing constraints?
02-05-2009 07:21 PM
Only external clock could be used in OFFSET constraints.Please see the WP237 for more information.