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Visitor sardman
Visitor
7,061 Views
Registered: ‎01-30-2009

OFFSET constraints and multicycle paths

Hello,

we need your support to set our timing constraints. As shown in this picture we have to drive a DEV by a DEV_CLK which is generated from the FPGA. The DEV Interface enable has also the same period of DEV_CLK. We tried to use these command lines in according with timing temporization:

 

NET "FEEDBACK" TNM_NET = "FEEDBACK";
TIMESPEC "TS_FEEDBACK" = PERIOD "FEEDBACK" 20 ns HIGH 10 ns;

 

TIMEGRP "DEV_in" OFFSET = IN 19 ns AFTER "DEV_CLK";

TIMEGRP "DEV_out" OFFSET = OUT 4 ns BEFORE "DEV_CLK"

 

with also,

 

TIMESPEC "TS_DEV" = FROM "DEV_IN" TO "DEV_IN": FEEDBACK*2;

 

The problem is that ISE couldn't accept the OFFSET command through an output clock signal and ignored a TIMESPEC command like that.

So, which is the right technique to set these kind of timing constraints?

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2 Replies
Participant jared.chen
Participant
6,989 Views
Registered: ‎05-12-2008

Re: OFFSET constraints and multicycle paths

Hello,

 

Only external clock could be used in OFFSET constraints.Please see the WP237 for more information.

Here is a link http://www.xilinx.com/support/documentation/white_papers/wp237.pdf

 

Regards,

Jared

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Xilinx Employee
Xilinx Employee
6,825 Views
Registered: ‎08-10-2008

Re: OFFSET constraints and multicycle paths

Only Pad clock can be the reference pin for Offset out constraint
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