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airizar
Observer
Observer
7,220 Views
Registered: ‎01-29-2009

OFFSET resctrictions and DCM

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Hi all,

I get the following warning by ngdbuild. I'm using xst as the VHDL compiler.

WARNING:ConstraintSystem:168 - Constraint <NET: UniqueName:
   /fpga_cf_dn_rb_wg_ac_pf/EXPANDED/din<11> OFFSET = IN 7000 ps BEFORE
   "clk_140">: This constraint will be ignored because NET "clk_140" could not
   be found or was not connected to a PAD.

My system has an input clock of 140 MHz that is feed into a DCM block that halves the frequency.
I used two clocks in my design called clk_140 and clk_70, and both of the are outputs of the DCM block.

The input and output data of my design are clocked in my VHDL description at 140 MHz, so i'm usign the clk_140 clock.
But when specifiying an OFFSET IN or OFFSET OUT restriction, the synthesizer says that pads can only be  clocked by input clocks and therefore ignores them.

How can I specify OFFSET restrictions in my design?

Regards

Andoni

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barriet
Xilinx Employee
Xilinx Employee
8,027 Views
Registered: ‎08-13-2007

The OFSET IN constraint references an external data to clock relationship.

In other words, you need to use the name of the clock input pad (your 140MHz clock input net at the input pad) - not the internal net that is your140MHz output from the DCM.

 

You may find this useful:

http://www.xilinx.com/support/documentation/white_papers/wp237.pdf (What are OFFSET Constraints?)

bt

View solution in original post

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barriet
Xilinx Employee
Xilinx Employee
8,028 Views
Registered: ‎08-13-2007

The OFSET IN constraint references an external data to clock relationship.

In other words, you need to use the name of the clock input pad (your 140MHz clock input net at the input pad) - not the internal net that is your140MHz output from the DCM.

 

You may find this useful:

http://www.xilinx.com/support/documentation/white_papers/wp237.pdf (What are OFFSET Constraints?)

bt

View solution in original post

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