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Contributor
Contributor
248 Views
Registered: ‎04-19-2016

OSERDESE2 tristate timing

The T1 input to OSERDESE2 seems to have use the CLK input as a destination clock for timing analysis, rather than CLKDIV input. Shouldn't it be the same as the data inputs?

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Xilinx Employee
Xilinx Employee
202 Views
Registered: ‎05-14-2008

Re: OSERDESE2 tristate timing

What is returned if you run below command in the tcl console in the implemented design?

get_timing_arcs -of [get_pins <T1 pin name of the OSERDESE2 cell>]

-vivian

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Contributor
Contributor
194 Views
Registered: ‎04-19-2016

Re: OSERDESE2 tristate timing

get_timing_arcs -of [get_cells {tx/io_inst[0].oserdes_cm}]
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/TQ [Reg Clk to Q] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/TCE [hold] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/TCE [setup] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/T1 [hold] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/T1 [setup] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/OQ [Reg Clk to Q] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/OCE [hold] }
{tx/io_inst[0].oserdes_cm/CLK --> tx/io_inst[0].oserdes_cm/OCE [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/RST [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/RST [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D8 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D8 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D7 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D7 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D6 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D6 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D5 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D5 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D4 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D4 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D3 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D3 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D2 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D2 [setup] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D1 [hold] }
{tx/io_inst[0].oserdes_cm/CLKDIV --> tx/io_inst[0].oserdes_cm/D1 [setup] }

 Unsurprisingly the timing on the T1 input is very hard to meet. Does it actually let you tristate the output part way through a word? If so how do you align it with the output? I would like to tristate the output on a word boundary ideally.

 

Here's the instantiation:

OBUFTDS obufds (
    .O(d_p[i]),
    .OB(d_n[i]),
    .I(OQ),
    .T(TQ)
);
OSERDESE2 #(
    .DATA_WIDTH(10),
    .TRISTATE_WIDTH(1),
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("SDR"),
    .SERDES_MODE("MASTER")
) oserdes_cm (
    .OQ       	(OQ),
    .OCE     	(1'b1),
    .CLK    	(tx_clk),
    .RST     	(reset),
    .CLKDIV  	(data_clk),
    .D8  		(d[7]),
    .D7  		(d[6]),
    .D6  		(d[5]),
    .D5  		(d[4]),
    .D4  		(d[3]),
    .D3  		(d[2]),
    .D2  		(d[1]),
    .D1  		(d[0]),
    .TQ  		(TQ),
    .T1 		(!en),
    .T2 		(1'b0),
    .T3 		(1'b0),
    .T4 		(1'b0),
    .TCE	 	(1'b1),
    .TBYTEIN	(1'b0),
    .TBYTEOUT	(),
    .OFB	 	(),
    .TFB	 	(),
    .SHIFTOUT1 	(),
    .SHIFTOUT2 	(),
    .SHIFTIN1 	(shift[0]),
    .SHIFTIN2 	(shift[1])
);

OSERDESE2 #(
    .DATA_WIDTH(10),
    .TRISTATE_WIDTH(1),
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("SDR"),
    .SERDES_MODE("SLAVE")
) oserdes_cs (
    .OQ       	(),
    .OCE     	(1'b1),
    .CLK    	(tx_clk),
    .RST     	(reset),
    .CLKDIV  	(data_clk),
    .D8  		(1'b0),
    .D7  		(1'b0),
    .D6  		(1'b0),
    .D5  		(1'b0),
    .D4  		(d[9]),
    .D3  		(d[8]),
    .D2  		(1'b0),
    .D1  		(1'b0),
    .TQ  		(),
    .T1 		(1'b0),
    .T2 		(1'b0),
    .T3 		(1'b0),
    .T4 		(1'b0),
    .TCE	 	(1'b1),
    .TBYTEIN	(1'b0),
    .TBYTEOUT	(),
    .OFB	 	(),
    .TFB	 	(),
    .SHIFTOUT1 	(shift[0]),
    .SHIFTOUT2 	(shift[1]),
    .SHIFTIN1 	(1'b0),
    .SHIFTIN2 	(1'b0)
);
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Xilinx Employee
Xilinx Employee
177 Views
Registered: ‎05-14-2008

Re: OSERDESE2 tristate timing

Could you post your timing report that shows the timing error on the T1 pin?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Contributor
Contributor
128 Views
Registered: ‎04-19-2016

Re: OSERDESE2 tristate timing

Sorry for the delay getting back to you, I had 'fixed' it temporarily by moving some IOs around and didn't have the failing report to hand. Here it is:

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date         : Wed Aug 14 15:37:04 2019
| Host         : DESKTOP-5E7FDE1 running 64-bit major release  (build 9200)
| Command      : report_timing -from [get_pins tx_en_reg/C] -to [get_pins {tx/io_inst[5].oserdes_cm/T1}] -delay_type min_max -max_paths 10 -sort_by group -input_pins -routable_nets -name timing_1 -return_string
| Design       : top
| Device       : 7s25-csga225
| Speed File   : -2  PRODUCTION 1.23 2018-06-13
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) :        -0.106ns  (required time - arrival time)
  Source:                 tx_en_reg/C
                            (rising edge-triggered cell FDRE clocked by data_clk  {rise@0.000ns fall@4.000ns period=10.000ns})
  Destination:            tx/io_inst[5].oserdes_cm/T1
                            (rising edge-triggered cell OSERDESE2 clocked by clk  {rise@0.000ns fall@1.000ns period=2.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.000ns  (clk rise@2.000ns - data_clk rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.379ns (29.353%)  route 0.912ns (70.647%))
  Logic Levels:           0  
  Clock Path Skew:        -0.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.589ns = ( 4.589 - 2.000 ) 
    Source Clock Delay      (SCD):    2.683ns
    Clock Pessimism Removal (CPR):    0.038ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock data_clk rise edge)
                                                                    0.000     0.000 r  
                  H1                                                0.000     0.000 r  z2s_clk_p (IN)
                                       net (fo=1, unset)            0.000     0.000    clk_ibuf/i
                  H1                                                                r  clk_ibuf/IBUFDS_M/I
                  H1                   IBUFDS_INTERMDISABLE_INT (Prop_ibufds_intermdisable_int_I_O)
                                                                    0.818     0.818 r  clk_ibuf/IBUFDS_M/O
                                       net (fo=6, routed)           0.449     1.267    refclk
                  BUFR_X1Y1                                                         r  serdes_bufr2/I
                  BUFR_X1Y1            BUFR (Prop_bufr_I_O)         0.757     2.024 r  serdes_bufr2/O
                                       net (fo=160, routed)         0.659     2.683    data_clk
                  SLICE_X41Y17         FDRE                                         r  tx_en_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X41Y17         FDRE (Prop_fdre_C_Q)         0.379     3.062 f  tx_en_reg/Q
                                       net (fo=6, routed)           0.912     3.974    tx/tx_en
    Placement     OLOGIC_X1Y38         OSERDESE2                                    r  tx/io_inst[5].oserdes_cm/T1  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk rise edge)        2.000     2.000 r  
                  H1                                                0.000     2.000 r  z2s_clk_p (IN)
                                       net (fo=1, unset)            0.000     2.000    clk_ibuf/i
                  H1                                                                r  clk_ibuf/IBUFDS_M/I
                  H1                   IBUFDS_INTERMDISABLE_INT (Prop_ibufds_intermdisable_int_I_O)
                                                                    0.780     2.780 r  clk_ibuf/IBUFDS_M/O
                                       net (fo=6, routed)           0.341     3.121    refclk
                  BUFIO_X1Y2                                                        r  rx_clk_bufio/I
                  BUFIO_X1Y2           BUFIO (Prop_bufio_I_O)       1.224     4.345 r  rx_clk_bufio/O
                                       net (fo=32, routed)          0.244     4.589    tx/clk_500
                  OLOGIC_X1Y38         OSERDESE2                                    r  tx/io_inst[5].oserdes_cm/CLK
                                       clock pessimism              0.038     4.627    
                                       clock uncertainty           -0.035     4.591    
                  OLOGIC_X1Y38         OSERDESE2 (Setup_oserdese2_CLK_T1)
                                                                   -0.723     3.868    tx/io_inst[5].oserdes_cm
  ---------------------------------------------------------------------------------
                                       required time                          3.868    
                                       arrival time                          -3.974    
  ---------------------------------------------------------------------------------
                                       slack                                 -0.106    

Slack (MET) :             0.565ns  (arrival time - required time)
  Source:                 tx_en_reg/C
                            (rising edge-triggered cell FDRE clocked by data_clk  {rise@0.000ns fall@4.000ns period=10.000ns})
  Destination:            tx/io_inst[5].oserdes_cm/T1
                            (rising edge-triggered cell OSERDESE2 clocked by clk  {rise@0.000ns fall@1.000ns period=2.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - data_clk rise@0.000ns)
  Data Path Delay:        0.621ns  (logic 0.141ns (22.699%)  route 0.480ns (77.301%))
  Logic Levels:           0  
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.319ns
    Source Clock Delay      (SCD):    1.113ns
    Clock Pessimism Removal (CPR):    0.037ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock data_clk rise edge)
                                                                    0.000     0.000 r  
                  H1                                                0.000     0.000 r  z2s_clk_p (IN)
                                       net (fo=1, unset)            0.000     0.000    clk_ibuf/i
                  H1                                                                r  clk_ibuf/IBUFDS_M/I
                  H1                   IBUFDS_INTERMDISABLE_INT (Prop_ibufds_intermdisable_int_I_O)
                                                                    0.377     0.377 r  clk_ibuf/IBUFDS_M/O
                                       net (fo=6, routed)           0.206     0.583    refclk
                  BUFR_X1Y1                                                         r  serdes_bufr2/I
                  BUFR_X1Y1            BUFR (Prop_bufr_I_O)         0.271     0.854 r  serdes_bufr2/O
                                       net (fo=160, routed)         0.259     1.113    data_clk
                  SLICE_X41Y17         FDRE                                         r  tx_en_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X41Y17         FDRE (Prop_fdre_C_Q)         0.141     1.254 f  tx_en_reg/Q
                                       net (fo=6, routed)           0.480     1.734    tx/tx_en
    Placement     OLOGIC_X1Y38         OSERDESE2                                    r  tx/io_inst[5].oserdes_cm/T1  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk rise edge)        0.000     0.000 r  
                  H1                                                0.000     0.000 r  z2s_clk_p (IN)
                                       net (fo=1, unset)            0.000     0.000    clk_ibuf/i
                  H1                                                                r  clk_ibuf/IBUFDS_M/I
                  H1                   IBUFDS_INTERMDISABLE_INT (Prop_ibufds_intermdisable_int_I_O)
                                                                    0.414     0.414 r  clk_ibuf/IBUFDS_M/O
                                       net (fo=6, routed)           0.280     0.694    refclk
                  BUFIO_X1Y2                                                        r  rx_clk_bufio/I
                  BUFIO_X1Y2           BUFIO (Prop_bufio_I_O)       0.517     1.211 r  rx_clk_bufio/O
                                       net (fo=32, routed)          0.108     1.319    tx/clk_500
                  OLOGIC_X1Y38         OSERDESE2                                    r  tx/io_inst[5].oserdes_cm/CLK
                                       clock pessimism             -0.037     1.282    
                  OLOGIC_X1Y38         OSERDESE2 (Hold_oserdese2_CLK_T1)
                                                                   -0.113     1.169    tx/io_inst[5].oserdes_cm
  ---------------------------------------------------------------------------------
                                       required time                         -1.169    
                                       arrival time                           1.734    
  ---------------------------------------------------------------------------------
                                       slack                                  0.565    




The clocks are derived from an input pin at 500MHz, z2s_clk_p, which is buffered through a BUFIO to create clk_500 and a divide-by-5 BUFR to create data_clk. Those are clocking a 10:1 OSERDESE2 instantiated as in an earlier post.

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