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Visitor yys@n
Visitor
935 Views
Registered: ‎07-25-2018

Output Delays for Source-Synchronous Center-Sampled Generated Forwarded Clock

Hello everyone,

 

This question is very similar to others on this forum, but there's a particular feature that I just can't figure out.

 

I am trying to constrain the output delay on a source-synchronous interface out of the FPGA. The forwarded clock is generated from the system clock divided by two. The same VHDL code that creates this forwarded clock (on the rising edge of the system clock, invert the forwarded clock - fairly typical divide-by-2 structure) also generates data every time the forwarded clock goes from high to low. This data is sent out of the FPGA to an ADC (whose setup and hold times I wish to represent as output delays) - the ADC reads the data on the rising edge of the forwarded clock: this data is thus center-sampled. I have IOBs on all my outputs.

 

My issue is that I can't figure out how to correctly write the constraints for this. This setup fails timing (specifically hold timing), and the path report indicates that Vivado puts the rising edge of both the system clock and the forwarded clock at 0ns. This is not true, as the data is center-sampled.

 

The only way I've made this pass timing was by putting a multicycle constraint from the system clock to the generated forwarded clock where I set hold to "1". My reasoning for this is that this will push the hold check to the next cycle of the system clock, which is where the rising edge of the forwarded clock is.

 

Is this correct? Or is there something else I should be doing? I've seen some reports that I should be using false path constraints or something like that.

 

Included below: a sketch of the output port structure, the output port waveform, and some existing constraints.

 

2018-11-02 17_15_07-Drawing1 - Visio Professional.png

wavedrom2222.png

 

# Create generated forwarded clock from IOB clock input

create_generated_clock -name SCKO -source [get_pins X_Block/X_inst/SCKO_reg/C] -divide_by 2 [get_ports SCKO]

# Setup: 2ns, Hold: 1ns

set_output_delay -clock [get_clocks SCKO] -min -add_delay -1.0 [get_ports SDO]
set_output_delay -clock [get_clocks SCKO] -max -add_delay 2.0 [get_ports SDO]

# ATTEMPT: Push hold to rising edge of SCKO?

set_multicycle_path 1 -hold -from [get_clocks SYS_CLK] -to [get_clocks SCKO]

 

----

 

Thanks!

 

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Visitor yys@n
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412 Views
Registered: ‎07-25-2018

Re: Output Delays for Source-Synchronous Center-Sampled Generated Forwarded Clock

After further review, I believe that setting the multicycle's hold multiplier to 1 (as done in the original post) is the only way to do this.

 

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