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Adventurer
Adventurer
1,929 Views
Registered: ‎01-15-2013

Output constrain for synchronous data transfer (SDR)

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Hi,

 

I would like to interface my FPGA with an external synchronous element. The data is generated in a clock domain and I feed the same clock as the output clock to the external chip (SDR). I do not use a PLL to generate a phase shifted clock. I need to run at 100 MHz. I know the setup(1.5 ns) and hold time(0.8ns)  requirements of the external device. 

 

I assume I should use maximum/minimum output delay constrain but I am not sure if I calculated it properly. 

 

output maximum delay value = maximum trace delay for data+  setup time of external register - minimum trace delay for clock

output minimum delay value =  minimum trace delay for data - hold time of external register - maximum trace delay for clock

 

As an example, I assumed minimum trace of clock and data to be 0.2 ns and maximum trace of clock and data to be 0.5 ns. 

Then I get output maximum and minimum delay to be 1.8 ns and -0.8 ns. 

 

It would be great if someone can validate my calculations and suggest any other alternatives for constrain if any. 

 

Thanks,

Paul 

 

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Guide
Guide
3,182 Views
Registered: ‎01-23-2009

No, this isn't right...

 

The modified setup time is the original_setup_time + maximum_data_delay - minimum_clock_delay

The modified hold time is          original_hold_time + maximum_clock_delay - minimum_data_delay

 

So your modified setup time is 1.5+0.5-0.2= 1.8ns

Your modified hold time is 0.8+0.5-0.2 = 1.1ns

 

So your constraints are

 

set_output_delay -max 1.8

set_output_delay -min -1.1

 

As a general rule nothing gets better in the case where there is uncertainty - uncertainty always hurts. In this case, you have 0.3ns of uncertainty between the clock and data routing, so this costs you 0.3ns of extra hold requirement and 0.3ns of extra setup requirement.

 

Avrum

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Highlighted
Guide
Guide
3,183 Views
Registered: ‎01-23-2009

No, this isn't right...

 

The modified setup time is the original_setup_time + maximum_data_delay - minimum_clock_delay

The modified hold time is          original_hold_time + maximum_clock_delay - minimum_data_delay

 

So your modified setup time is 1.5+0.5-0.2= 1.8ns

Your modified hold time is 0.8+0.5-0.2 = 1.1ns

 

So your constraints are

 

set_output_delay -max 1.8

set_output_delay -min -1.1

 

As a general rule nothing gets better in the case where there is uncertainty - uncertainty always hurts. In this case, you have 0.3ns of uncertainty between the clock and data routing, so this costs you 0.3ns of extra hold requirement and 0.3ns of extra setup requirement.

 

Avrum

View solution in original post